This is the 4.9.150 stable release
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This commit is contained in:
commit
c7b283dd04
2
Makefile
2
Makefile
|
@ -1,6 +1,6 @@
|
|||
VERSION = 4
|
||||
PATCHLEVEL = 9
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||||
SUBLEVEL = 149
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SUBLEVEL = 150
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EXTRAVERSION =
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NAME = Roaring Lionus
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||||
|
||||
|
|
|
@ -117,13 +117,17 @@
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compatible = "regulator-fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
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clock-names = "slow";
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regulator-name = "reg_wlan";
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startup-delay-us = <70000>;
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gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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usdhc2_pwrseq: usdhc2_pwrseq {
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compatible = "mmc-pwrseq-simple";
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clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
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clock-names = "ext_clock";
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};
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};
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&adc1 {
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|
@ -430,6 +434,7 @@
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bus-width = <4>;
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non-removable;
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vmmc-supply = <®_wlan>;
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mmc-pwrseq = <&usdhc2_pwrseq>;
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cap-power-off-card;
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keep-power-in-suspend;
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status = "okay";
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|
|
|
@ -108,7 +108,7 @@ int __init imx6sx_cpuidle_init(void)
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* except for power up sw2iso which need to be
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* larger than LDO ramp up time.
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*/
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imx_gpc_set_arm_power_up_timing(2, 1);
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imx_gpc_set_arm_power_up_timing(0xf, 1);
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imx_gpc_set_arm_power_down_timing(1, 1);
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return cpuidle_register(&imx6sx_cpuidle_driver, NULL);
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|
|
|
@ -111,7 +111,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
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/* Map delay slot emulation page */
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base = mmap_region(NULL, STACK_TOP, PAGE_SIZE,
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VM_READ|VM_WRITE|VM_EXEC|
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VM_READ | VM_EXEC |
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC,
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0);
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if (IS_ERR_VALUE(base)) {
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|
|
|
@ -211,8 +211,9 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
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{
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int isa16 = get_isa16_mode(regs->cp0_epc);
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mips_instruction break_math;
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struct emuframe __user *fr;
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int err, fr_idx;
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unsigned long fr_uaddr;
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struct emuframe fr;
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int fr_idx, ret;
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/* NOP is easy */
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if (ir == 0)
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|
@ -247,27 +248,31 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
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fr_idx = alloc_emuframe();
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if (fr_idx == BD_EMUFRAME_NONE)
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return SIGBUS;
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fr = &dsemul_page()[fr_idx];
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/* Retrieve the appropriately encoded break instruction */
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break_math = BREAK_MATH(isa16);
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/* Write the instructions to the frame */
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if (isa16) {
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err = __put_user(ir >> 16,
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(u16 __user *)(&fr->emul));
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err |= __put_user(ir & 0xffff,
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(u16 __user *)((long)(&fr->emul) + 2));
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err |= __put_user(break_math >> 16,
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(u16 __user *)(&fr->badinst));
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err |= __put_user(break_math & 0xffff,
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(u16 __user *)((long)(&fr->badinst) + 2));
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union mips_instruction _emul = {
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.halfword = { ir >> 16, ir }
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};
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union mips_instruction _badinst = {
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.halfword = { break_math >> 16, break_math }
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};
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fr.emul = _emul.word;
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fr.badinst = _badinst.word;
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} else {
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err = __put_user(ir, &fr->emul);
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err |= __put_user(break_math, &fr->badinst);
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fr.emul = ir;
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fr.badinst = break_math;
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}
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if (unlikely(err)) {
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/* Write the frame to user memory */
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fr_uaddr = (unsigned long)&dsemul_page()[fr_idx];
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ret = access_process_vm(current, fr_uaddr, &fr, sizeof(fr),
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FOLL_FORCE | FOLL_WRITE);
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if (unlikely(ret != sizeof(fr))) {
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MIPS_FPU_EMU_INC_STATS(errors);
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free_emuframe(fr_idx, current->mm);
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return SIGBUS;
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|
@ -279,10 +284,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
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atomic_set(¤t->thread.bd_emu_frame, fr_idx);
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/* Change user register context to execute the frame */
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regs->cp0_epc = (unsigned long)&fr->emul | isa16;
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/* Ensure the icache observes our newly written frame */
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flush_cache_sigtramp((unsigned long)&fr->emul);
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regs->cp0_epc = fr_uaddr | isa16;
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return 0;
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}
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|
|
|
@ -15,7 +15,7 @@
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RELA = 7
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RELACOUNT = 0x6ffffff9
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.text
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.data
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/* A procedure descriptor used when booting this as a COFF file.
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* When making COFF, this comes first in the link and we're
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* linked at 0x500000.
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|
@ -23,6 +23,8 @@ RELACOUNT = 0x6ffffff9
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.globl _zimage_start_opd
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_zimage_start_opd:
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.long 0x500000, 0, 0, 0
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.text
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b _zimage_start
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#ifdef __powerpc64__
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.balign 8
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|
|
|
@ -866,7 +866,23 @@ static long restore_tm_user_regs(struct pt_regs *regs,
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/* If TM bits are set to the reserved value, it's an invalid context */
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if (MSR_TM_RESV(msr_hi))
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return 1;
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/* Pull in the MSR TM bits from the user context */
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/*
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* Disabling preemption, since it is unsafe to be preempted
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* with MSR[TS] set without recheckpointing.
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*/
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preempt_disable();
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/*
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* CAUTION:
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* After regs->MSR[TS] being updated, make sure that get_user(),
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* put_user() or similar functions are *not* called. These
|
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* functions can generate page faults which will cause the process
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* to be de-scheduled with MSR[TS] set but without calling
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* tm_recheckpoint(). This can cause a bug.
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*
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* Pull in the MSR TM bits from the user context
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*/
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regs->msr = (regs->msr & ~MSR_TS_MASK) | (msr_hi & MSR_TS_MASK);
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/* Now, recheckpoint. This loads up all of the checkpointed (older)
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* registers, including FP and V[S]Rs. After recheckpointing, the
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|
@ -891,6 +907,8 @@ static long restore_tm_user_regs(struct pt_regs *regs,
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}
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#endif
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preempt_enable();
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return 0;
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}
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#endif
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|
|
|
@ -452,20 +452,6 @@ static long restore_tm_sigcontexts(struct task_struct *tsk,
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if (MSR_TM_RESV(msr))
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return -EINVAL;
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/* pull in MSR TS bits from user context */
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regs->msr = (regs->msr & ~MSR_TS_MASK) | (msr & MSR_TS_MASK);
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/*
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* Ensure that TM is enabled in regs->msr before we leave the signal
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* handler. It could be the case that (a) user disabled the TM bit
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* through the manipulation of the MSR bits in uc_mcontext or (b) the
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* TM bit was disabled because a sufficient number of context switches
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* happened whilst in the signal handler and load_tm overflowed,
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* disabling the TM bit. In either case we can end up with an illegal
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* TM state leading to a TM Bad Thing when we return to userspace.
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*/
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regs->msr |= MSR_TM;
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/* pull in MSR LE from user context */
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regs->msr = (regs->msr & ~MSR_LE) | (msr & MSR_LE);
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|
@ -557,6 +543,34 @@ static long restore_tm_sigcontexts(struct task_struct *tsk,
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tm_enable();
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/* Make sure the transaction is marked as failed */
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tsk->thread.tm_texasr |= TEXASR_FS;
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/*
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* Disabling preemption, since it is unsafe to be preempted
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* with MSR[TS] set without recheckpointing.
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*/
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preempt_disable();
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/* pull in MSR TS bits from user context */
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regs->msr = (regs->msr & ~MSR_TS_MASK) | (msr & MSR_TS_MASK);
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/*
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* Ensure that TM is enabled in regs->msr before we leave the signal
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* handler. It could be the case that (a) user disabled the TM bit
|
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* through the manipulation of the MSR bits in uc_mcontext or (b) the
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* TM bit was disabled because a sufficient number of context switches
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* happened whilst in the signal handler and load_tm overflowed,
|
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* disabling the TM bit. In either case we can end up with an illegal
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* TM state leading to a TM Bad Thing when we return to userspace.
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*
|
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* CAUTION:
|
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* After regs->MSR[TS] being updated, make sure that get_user(),
|
||||
* put_user() or similar functions are *not* called. These
|
||||
* functions can generate page faults which will cause the process
|
||||
* to be de-scheduled with MSR[TS] set but without calling
|
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* tm_recheckpoint(). This can cause a bug.
|
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*/
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regs->msr |= MSR_TM;
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/* This loads the checkpointed FP/VEC state, if used */
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tm_recheckpoint(&tsk->thread, msr);
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|
@ -570,6 +584,8 @@ static long restore_tm_sigcontexts(struct task_struct *tsk,
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regs->msr |= MSR_VEC;
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}
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preempt_enable();
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return err;
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}
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#endif
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|
|
|
@ -77,6 +77,7 @@ static int chacha20_simd(struct blkcipher_desc *desc, struct scatterlist *dst,
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blkcipher_walk_init(&walk, dst, src, nbytes);
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err = blkcipher_walk_virt_block(desc, &walk, CHACHA_BLOCK_SIZE);
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desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
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crypto_chacha_init(state, crypto_blkcipher_ctx(desc->tfm), walk.iv);
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|
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|
|
|
@ -352,6 +352,7 @@ static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
|
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if (vc4_state->is_unity)
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vc4_state->x_scaling[0] = VC4_SCALING_PPF;
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} else {
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vc4_state->is_yuv = false;
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vc4_state->x_scaling[1] = VC4_SCALING_NONE;
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vc4_state->y_scaling[1] = VC4_SCALING_NONE;
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}
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|
|
|
@ -1429,7 +1429,8 @@ nr_pages_store(struct device *dev, struct device_attribute *attr,
|
|||
if (!end)
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break;
|
||||
|
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len -= end - p;
|
||||
/* consume the number and the following comma, hence +1 */
|
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len -= end - p + 1;
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p = end + 1;
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} while (len);
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|
||||
|
|
|
@ -1088,6 +1088,8 @@ int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
|
|||
|
||||
if (slen > len)
|
||||
slen = len;
|
||||
if (slen > ss->sge.sge_length)
|
||||
slen = ss->sge.sge_length;
|
||||
update_sge(ss, slen);
|
||||
seg_pio_copy_mid(pbuf, addr, slen);
|
||||
len -= slen;
|
||||
|
|
|
@ -826,11 +826,16 @@ static enum resp_states do_complete(struct rxe_qp *qp,
|
|||
|
||||
memset(&cqe, 0, sizeof(cqe));
|
||||
|
||||
wc->wr_id = wqe->wr_id;
|
||||
if (qp->rcq->is_user) {
|
||||
uwc->status = qp->resp.status;
|
||||
uwc->qp_num = qp->ibqp.qp_num;
|
||||
uwc->wr_id = wqe->wr_id;
|
||||
} else {
|
||||
wc->status = qp->resp.status;
|
||||
wc->qp = &qp->ibqp;
|
||||
wc->wr_id = wqe->wr_id;
|
||||
}
|
||||
|
||||
/* fields after status are not required for errors */
|
||||
if (wc->status == IB_WC_SUCCESS) {
|
||||
wc->opcode = (pkt->mask & RXE_IMMDT_MASK &&
|
||||
pkt->mask & RXE_WRITE_MASK) ?
|
||||
|
|
|
@ -126,12 +126,8 @@ static irqreturn_t omap4_keypad_irq_handler(int irq, void *dev_id)
|
|||
{
|
||||
struct omap4_keypad *keypad_data = dev_id;
|
||||
|
||||
if (kbd_read_irqreg(keypad_data, OMAP4_KBD_IRQSTATUS)) {
|
||||
/* Disable interrupts */
|
||||
kbd_write_irqreg(keypad_data, OMAP4_KBD_IRQENABLE,
|
||||
OMAP4_VAL_IRQDISABLE);
|
||||
if (kbd_read_irqreg(keypad_data, OMAP4_KBD_IRQSTATUS))
|
||||
return IRQ_WAKE_THREAD;
|
||||
}
|
||||
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
@ -173,11 +169,6 @@ static irqreturn_t omap4_keypad_irq_thread_fn(int irq, void *dev_id)
|
|||
kbd_write_irqreg(keypad_data, OMAP4_KBD_IRQSTATUS,
|
||||
kbd_read_irqreg(keypad_data, OMAP4_KBD_IRQSTATUS));
|
||||
|
||||
/* enable interrupts */
|
||||
kbd_write_irqreg(keypad_data, OMAP4_KBD_IRQENABLE,
|
||||
OMAP4_DEF_IRQENABLE_EVENTEN |
|
||||
OMAP4_DEF_IRQENABLE_LONGKEY);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
@ -214,9 +205,10 @@ static void omap4_keypad_close(struct input_dev *input)
|
|||
|
||||
disable_irq(keypad_data->irq);
|
||||
|
||||
/* Disable interrupts */
|
||||
/* Disable interrupts and wake-up events */
|
||||
kbd_write_irqreg(keypad_data, OMAP4_KBD_IRQENABLE,
|
||||
OMAP4_VAL_IRQDISABLE);
|
||||
kbd_writel(keypad_data, OMAP4_KBD_WAKEUPENABLE, 0);
|
||||
|
||||
/* clear pending interrupts */
|
||||
kbd_write_irqreg(keypad_data, OMAP4_KBD_IRQSTATUS,
|
||||
|
@ -364,7 +356,7 @@ static int omap4_keypad_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
error = request_threaded_irq(keypad_data->irq, omap4_keypad_irq_handler,
|
||||
omap4_keypad_irq_thread_fn, 0,
|
||||
omap4_keypad_irq_thread_fn, IRQF_ONESHOT,
|
||||
"omap4-keypad", keypad_data);
|
||||
if (error) {
|
||||
dev_err(&pdev->dev, "failed to register interrupt\n");
|
||||
|
|
|
@ -2084,7 +2084,7 @@ static int domain_context_mapping_one(struct dmar_domain *domain,
|
|||
* than default. Unnecessary for PT mode.
|
||||
*/
|
||||
if (translation != CONTEXT_TT_PASS_THROUGH) {
|
||||
for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
|
||||
for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) {
|
||||
ret = -ENOMEM;
|
||||
pgd = phys_to_virt(dma_pte_addr(pgd));
|
||||
if (!dma_pte_present(pgd))
|
||||
|
@ -2098,7 +2098,7 @@ static int domain_context_mapping_one(struct dmar_domain *domain,
|
|||
translation = CONTEXT_TT_MULTI_LEVEL;
|
||||
|
||||
context_set_address_root(context, virt_to_phys(pgd));
|
||||
context_set_address_width(context, iommu->agaw);
|
||||
context_set_address_width(context, agaw);
|
||||
} else {
|
||||
/*
|
||||
* In pass through mode, AW must be programmed to
|
||||
|
|
|
@ -217,7 +217,7 @@ u32 genwqe_crc32(u8 *buff, size_t len, u32 init)
|
|||
void *__genwqe_alloc_consistent(struct genwqe_dev *cd, size_t size,
|
||||
dma_addr_t *dma_handle)
|
||||
{
|
||||
if (get_order(size) > MAX_ORDER)
|
||||
if (get_order(size) >= MAX_ORDER)
|
||||
return NULL;
|
||||
|
||||
return dma_zalloc_coherent(&cd->pci_dev->dev, size, dma_handle,
|
||||
|
|
|
@ -29,9 +29,6 @@
|
|||
#define RES_RING_CSR 1
|
||||
#define RES_RING_CMD 2
|
||||
|
||||
static const struct of_device_id xgene_enet_of_match[];
|
||||
static const struct acpi_device_id xgene_enet_acpi_match[];
|
||||
|
||||
static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool)
|
||||
{
|
||||
struct xgene_enet_raw_desc16 *raw_desc;
|
||||
|
|
|
@ -1278,6 +1278,7 @@ enum sp_rtnl_flag {
|
|||
BNX2X_SP_RTNL_TX_STOP,
|
||||
BNX2X_SP_RTNL_GET_DRV_VERSION,
|
||||
BNX2X_SP_RTNL_CHANGE_UDP_PORT,
|
||||
BNX2X_SP_RTNL_UPDATE_SVID,
|
||||
};
|
||||
|
||||
enum bnx2x_iov_flag {
|
||||
|
|
|
@ -2925,6 +2925,10 @@ static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
|
|||
func_params.f_obj = &bp->func_obj;
|
||||
func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
|
||||
|
||||
/* Prepare parameters for function state transitions */
|
||||
__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
|
||||
__set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
|
||||
|
||||
if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
|
||||
int func = BP_ABS_FUNC(bp);
|
||||
u32 val;
|
||||
|
@ -4301,7 +4305,8 @@ static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
|
|||
bnx2x_handle_eee_event(bp);
|
||||
|
||||
if (val & DRV_STATUS_OEM_UPDATE_SVID)
|
||||
bnx2x_handle_update_svid_cmd(bp);
|
||||
bnx2x_schedule_sp_rtnl(bp,
|
||||
BNX2X_SP_RTNL_UPDATE_SVID, 0);
|
||||
|
||||
if (bp->link_vars.periodic_flags &
|
||||
PERIODIC_FLAGS_LINK_EVENT) {
|
||||
|
@ -8462,6 +8467,7 @@ int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
|
|||
/* Fill a user request section if needed */
|
||||
if (!test_bit(RAMROD_CONT, ramrod_flags)) {
|
||||
ramrod_param.user_req.u.vlan.vlan = vlan;
|
||||
__set_bit(BNX2X_VLAN, &ramrod_param.user_req.vlan_mac_flags);
|
||||
/* Set the command: ADD or DEL */
|
||||
if (set)
|
||||
ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
|
||||
|
@ -8482,6 +8488,27 @@ int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
|
|||
return rc;
|
||||
}
|
||||
|
||||
static int bnx2x_del_all_vlans(struct bnx2x *bp)
|
||||
{
|
||||
struct bnx2x_vlan_mac_obj *vlan_obj = &bp->sp_objs[0].vlan_obj;
|
||||
unsigned long ramrod_flags = 0, vlan_flags = 0;
|
||||
struct bnx2x_vlan_entry *vlan;
|
||||
int rc;
|
||||
|
||||
__set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
|
||||
__set_bit(BNX2X_VLAN, &vlan_flags);
|
||||
rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_flags, &ramrod_flags);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* Mark that hw forgot all entries */
|
||||
list_for_each_entry(vlan, &bp->vlan_reg, link)
|
||||
vlan->hw = false;
|
||||
bp->vlan_cnt = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int bnx2x_del_all_macs(struct bnx2x *bp,
|
||||
struct bnx2x_vlan_mac_obj *mac_obj,
|
||||
int mac_type, bool wait_for_comp)
|
||||
|
@ -9320,6 +9347,17 @@ void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
|
|||
BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
|
||||
rc);
|
||||
|
||||
/* The whole *vlan_obj structure may be not initialized if VLAN
|
||||
* filtering offload is not supported by hardware. Currently this is
|
||||
* true for all hardware covered by CHIP_IS_E1x().
|
||||
*/
|
||||
if (!CHIP_IS_E1x(bp)) {
|
||||
/* Remove all currently configured VLANs */
|
||||
rc = bnx2x_del_all_vlans(bp);
|
||||
if (rc < 0)
|
||||
BNX2X_ERR("Failed to delete all VLANs\n");
|
||||
}
|
||||
|
||||
/* Disable LLH */
|
||||
if (!CHIP_IS_E1(bp))
|
||||
REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
|
||||
|
@ -10342,6 +10380,9 @@ sp_rtnl_not_reset:
|
|||
&bp->sp_rtnl_state))
|
||||
bnx2x_update_mng_version(bp);
|
||||
|
||||
if (test_and_clear_bit(BNX2X_SP_RTNL_UPDATE_SVID, &bp->sp_rtnl_state))
|
||||
bnx2x_handle_update_svid_cmd(bp);
|
||||
|
||||
if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT,
|
||||
&bp->sp_rtnl_state)) {
|
||||
if (bnx2x_udp_port_update(bp)) {
|
||||
|
@ -11733,8 +11774,10 @@ static void bnx2x_get_fcoe_info(struct bnx2x *bp)
|
|||
* If maximum allowed number of connections is zero -
|
||||
* disable the feature.
|
||||
*/
|
||||
if (!bp->cnic_eth_dev.max_fcoe_conn)
|
||||
if (!bp->cnic_eth_dev.max_fcoe_conn) {
|
||||
bp->flags |= NO_FCOE_FLAG;
|
||||
eth_zero_addr(bp->fip_mac);
|
||||
}
|
||||
}
|
||||
|
||||
static void bnx2x_get_cnic_info(struct bnx2x *bp)
|
||||
|
@ -13005,13 +13048,6 @@ static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode)
|
|||
|
||||
int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
|
||||
{
|
||||
struct bnx2x_vlan_entry *vlan;
|
||||
|
||||
/* The hw forgot all entries after reload */
|
||||
list_for_each_entry(vlan, &bp->vlan_reg, link)
|
||||
vlan->hw = false;
|
||||
bp->vlan_cnt = 0;
|
||||
|
||||
/* Don't set rx mode here. Our caller will do it. */
|
||||
bnx2x_vlan_configure(bp, false);
|
||||
|
||||
|
|
|
@ -265,6 +265,7 @@ enum {
|
|||
BNX2X_ETH_MAC,
|
||||
BNX2X_ISCSI_ETH_MAC,
|
||||
BNX2X_NETQ_ETH_MAC,
|
||||
BNX2X_VLAN,
|
||||
BNX2X_DONT_CONSUME_CAM_CREDIT,
|
||||
BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
|
||||
};
|
||||
|
@ -272,7 +273,8 @@ enum {
|
|||
#define BNX2X_VLAN_MAC_CMP_MASK (1 << BNX2X_UC_LIST_MAC | \
|
||||
1 << BNX2X_ETH_MAC | \
|
||||
1 << BNX2X_ISCSI_ETH_MAC | \
|
||||
1 << BNX2X_NETQ_ETH_MAC)
|
||||
1 << BNX2X_NETQ_ETH_MAC | \
|
||||
1 << BNX2X_VLAN)
|
||||
#define BNX2X_VLAN_MAC_CMP_FLAGS(flags) \
|
||||
((flags) & BNX2X_VLAN_MAC_CMP_MASK)
|
||||
|
||||
|
|
|
@ -290,6 +290,9 @@ void hns_ae_stop(struct hnae_handle *handle)
|
|||
|
||||
hns_ae_ring_enable_all(handle, 0);
|
||||
|
||||
/* clean rx fbd. */
|
||||
hns_rcb_wait_fbd_clean(handle->qs, handle->q_num, RCB_INT_FLAG_RX);
|
||||
|
||||
(void)hns_mac_vm_config_bc_en(mac_cb, 0, false);
|
||||
}
|
||||
|
||||
|
|
|
@ -67,24 +67,30 @@ static void hns_gmac_enable(void *mac_drv, enum mac_commom_mode mode)
|
|||
struct mac_driver *drv = (struct mac_driver *)mac_drv;
|
||||
|
||||
/*enable GE rX/tX */
|
||||
if ((mode == MAC_COMM_MODE_TX) || (mode == MAC_COMM_MODE_RX_AND_TX))
|
||||
if (mode == MAC_COMM_MODE_TX || mode == MAC_COMM_MODE_RX_AND_TX)
|
||||
dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 1);
|
||||
|
||||
if ((mode == MAC_COMM_MODE_RX) || (mode == MAC_COMM_MODE_RX_AND_TX))
|
||||
if (mode == MAC_COMM_MODE_RX || mode == MAC_COMM_MODE_RX_AND_TX) {
|
||||
/* enable rx pcs */
|
||||
dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 0);
|
||||
dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 1);
|
||||
}
|
||||
}
|
||||
|
||||
static void hns_gmac_disable(void *mac_drv, enum mac_commom_mode mode)
|
||||
{
|
||||
struct mac_driver *drv = (struct mac_driver *)mac_drv;
|
||||
|
||||
/*disable GE rX/tX */
|
||||
if ((mode == MAC_COMM_MODE_TX) || (mode == MAC_COMM_MODE_RX_AND_TX))
|
||||
if (mode == MAC_COMM_MODE_TX || mode == MAC_COMM_MODE_RX_AND_TX)
|
||||
dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 0);
|
||||
|
||||
if ((mode == MAC_COMM_MODE_RX) || (mode == MAC_COMM_MODE_RX_AND_TX))
|
||||
if (mode == MAC_COMM_MODE_RX || mode == MAC_COMM_MODE_RX_AND_TX) {
|
||||
/* disable rx pcs */
|
||||
dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 1);
|
||||
dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/* hns_gmac_get_en - get port enable
|
||||
* @mac_drv:mac device
|
||||
|
|
|
@ -724,6 +724,17 @@ static void hns_mac_register_phy(struct hns_mac_cb *mac_cb)
|
|||
mac_cb->mac_id, addr);
|
||||
}
|
||||
|
||||
static void hns_mac_remove_phydev(struct hns_mac_cb *mac_cb)
|
||||
{
|
||||
if (!to_acpi_device_node(mac_cb->fw_port) || !mac_cb->phy_dev)
|
||||
return;
|
||||
|
||||
phy_device_remove(mac_cb->phy_dev);
|
||||
phy_device_free(mac_cb->phy_dev);
|
||||
|
||||
mac_cb->phy_dev = NULL;
|
||||
}
|
||||
|
||||
#define MAC_MEDIA_TYPE_MAX_LEN 16
|
||||
|
||||
static const struct {
|
||||
|
@ -1030,7 +1041,11 @@ void hns_mac_uninit(struct dsaf_device *dsaf_dev)
|
|||
int max_port_num = hns_mac_get_max_port_num(dsaf_dev);
|
||||
|
||||
for (i = 0; i < max_port_num; i++) {
|
||||
if (!dsaf_dev->mac_cb[i])
|
||||
continue;
|
||||
|
||||
dsaf_dev->misc_op->cpld_reset_led(dsaf_dev->mac_cb[i]);
|
||||
hns_mac_remove_phydev(dsaf_dev->mac_cb[i]);
|
||||
dsaf_dev->mac_cb[i] = NULL;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -2163,9 +2163,9 @@ void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num)
|
|||
DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
|
||||
|
||||
hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev,
|
||||
DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 0x80 * (u64)node_num);
|
||||
DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 4 * (u64)node_num);
|
||||
hw_stats->stp_drop += dsaf_read_dev(dsaf_dev,
|
||||
DSAF_INODE_IN_DATA_STP_DISC_0_REG + 0x80 * (u64)node_num);
|
||||
DSAF_INODE_IN_DATA_STP_DISC_0_REG + 4 * (u64)node_num);
|
||||
|
||||
/* pfc pause frame statistics stored in dsaf inode*/
|
||||
if ((node_num < DSAF_SERVICE_NW_NUM) && !is_ver1) {
|
||||
|
@ -2282,237 +2282,237 @@ void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
|
|||
DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4);
|
||||
p[223 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4);
|
||||
p[224 + i] = dsaf_read_dev(ddev,
|
||||
p[226 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4);
|
||||
}
|
||||
|
||||
p[227] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4);
|
||||
p[229] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4);
|
||||
|
||||
for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
|
||||
j = i * DSAF_COMM_CHN + port;
|
||||
p[228 + i] = dsaf_read_dev(ddev,
|
||||
p[230 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4);
|
||||
}
|
||||
|
||||
p[231] = dsaf_read_dev(ddev,
|
||||
DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 4);
|
||||
p[233] = dsaf_read_dev(ddev,
|
||||
DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 0x80);
|
||||
|
||||
/* dsaf inode registers */
|
||||
for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) {
|
||||
j = i * DSAF_COMM_CHN + port;
|
||||
p[232 + i] = dsaf_read_dev(ddev,
|
||||
p[234 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_CFG_REG_0_REG + j * 0x80);
|
||||
p[235 + i] = dsaf_read_dev(ddev,
|
||||
p[237 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80);
|
||||
p[238 + i] = dsaf_read_dev(ddev,
|
||||
p[240 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80);
|
||||
p[241 + i] = dsaf_read_dev(ddev,
|
||||
p[243 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80);
|
||||
p[244 + i] = dsaf_read_dev(ddev,
|
||||
p[246 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80);
|
||||
p[245 + i] = dsaf_read_dev(ddev,
|
||||
p[249 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80);
|
||||
p[248 + i] = dsaf_read_dev(ddev,
|
||||
p[252 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_BP_CNT_0_0_REG + j * 0x80);
|
||||
p[251 + i] = dsaf_read_dev(ddev,
|
||||
p[255 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_BP_CNT_1_0_REG + j * 0x80);
|
||||
p[254 + i] = dsaf_read_dev(ddev,
|
||||
p[258 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_BP_CNT_2_0_REG + j * 0x80);
|
||||
p[257 + i] = dsaf_read_dev(ddev,
|
||||
p[261 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_BP_CNT_3_0_REG + j * 0x80);
|
||||
p[260 + i] = dsaf_read_dev(ddev,
|
||||
p[264 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_INER_ST_0_REG + j * 0x80);
|
||||
p[263 + i] = dsaf_read_dev(ddev,
|
||||
p[267 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80);
|
||||
p[266 + i] = dsaf_read_dev(ddev,
|
||||
p[270 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80);
|
||||
p[269 + i] = dsaf_read_dev(ddev,
|
||||
p[273 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80);
|
||||
p[272 + i] = dsaf_read_dev(ddev,
|
||||
p[276 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80);
|
||||
p[275 + i] = dsaf_read_dev(ddev,
|
||||
p[279 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80);
|
||||
p[278 + i] = dsaf_read_dev(ddev,
|
||||
p[282 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80);
|
||||
p[281 + i] = dsaf_read_dev(ddev,
|
||||
p[285 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80);
|
||||
p[284 + i] = dsaf_read_dev(ddev,
|
||||
p[288 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80);
|
||||
p[287 + i] = dsaf_read_dev(ddev,
|
||||
p[291 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80);
|
||||
p[290 + i] = dsaf_read_dev(ddev,
|
||||
p[294 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80);
|
||||
p[293 + i] = dsaf_read_dev(ddev,
|
||||
p[297 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80);
|
||||
p[296 + i] = dsaf_read_dev(ddev,
|
||||
p[300 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80);
|
||||
p[299 + i] = dsaf_read_dev(ddev,
|
||||
p[303 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80);
|
||||
p[302 + i] = dsaf_read_dev(ddev,
|
||||
p[306 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80);
|
||||
p[305 + i] = dsaf_read_dev(ddev,
|
||||
p[309 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80);
|
||||
p[308 + i] = dsaf_read_dev(ddev,
|
||||
p[312 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80);
|
||||
}
|
||||
|
||||
/* dsaf onode registers */
|
||||
for (i = 0; i < DSAF_XOD_NUM; i++) {
|
||||
p[311 + i] = dsaf_read_dev(ddev,
|
||||
p[315 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90);
|
||||
p[319 + i] = dsaf_read_dev(ddev,
|
||||
p[323 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90);
|
||||
p[327 + i] = dsaf_read_dev(ddev,
|
||||
p[331 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90);
|
||||
p[335 + i] = dsaf_read_dev(ddev,
|
||||
p[339 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90);
|
||||
p[343 + i] = dsaf_read_dev(ddev,
|
||||
p[347 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90);
|
||||
p[351 + i] = dsaf_read_dev(ddev,
|
||||
p[355 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90);
|
||||
}
|
||||
|
||||
p[359] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90);
|
||||
p[360] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90);
|
||||
p[361] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90);
|
||||
p[363] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90);
|
||||
p[364] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90);
|
||||
p[365] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90);
|
||||
|
||||
for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) {
|
||||
j = i * DSAF_COMM_CHN + port;
|
||||
p[362 + i] = dsaf_read_dev(ddev,
|
||||
p[366 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_GNT_L_0_REG + j * 0x90);
|
||||
p[365 + i] = dsaf_read_dev(ddev,
|
||||
p[369 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_GNT_H_0_REG + j * 0x90);
|
||||
p[368 + i] = dsaf_read_dev(ddev,
|
||||
p[372 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90);
|
||||
p[371 + i] = dsaf_read_dev(ddev,
|
||||
p[375 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90);
|
||||
p[374 + i] = dsaf_read_dev(ddev,
|
||||
p[378 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90);
|
||||
p[377 + i] = dsaf_read_dev(ddev,
|
||||
p[381 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90);
|
||||
p[380 + i] = dsaf_read_dev(ddev,
|
||||
p[384 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90);
|
||||
p[383 + i] = dsaf_read_dev(ddev,
|
||||
p[387 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90);
|
||||
p[386 + i] = dsaf_read_dev(ddev,
|
||||
p[390 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90);
|
||||
p[389 + i] = dsaf_read_dev(ddev,
|
||||
p[393 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90);
|
||||
}
|
||||
|
||||
p[392] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90);
|
||||
p[393] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90);
|
||||
p[394] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90);
|
||||
p[395] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90);
|
||||
p[396] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90);
|
||||
DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90);
|
||||
p[397] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90);
|
||||
DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90);
|
||||
p[398] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90);
|
||||
DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90);
|
||||
p[399] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90);
|
||||
DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90);
|
||||
p[400] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90);
|
||||
DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90);
|
||||
p[401] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90);
|
||||
DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90);
|
||||
p[402] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90);
|
||||
DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90);
|
||||
p[403] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90);
|
||||
DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90);
|
||||
p[404] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90);
|
||||
p[405] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90);
|
||||
p[406] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90);
|
||||
p[407] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90);
|
||||
p[408] = dsaf_read_dev(ddev,
|
||||
DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90);
|
||||
|
||||
/* dsaf voq registers */
|
||||
for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) {
|
||||
j = (i * DSAF_COMM_CHN + port) * 0x90;
|
||||
p[405 + i] = dsaf_read_dev(ddev,
|
||||
p[409 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_VOQ_ECC_INVERT_EN_0_REG + j);
|
||||
p[408 + i] = dsaf_read_dev(ddev,
|
||||
p[412 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_VOQ_SRAM_PKT_NUM_0_REG + j);
|
||||
p[411 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j);
|
||||
p[414 + i] = dsaf_read_dev(ddev,
|
||||
p[415 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j);
|
||||
p[418 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_VOQ_OUT_PKT_NUM_0_REG + j);
|
||||
p[417 + i] = dsaf_read_dev(ddev,
|
||||
p[421 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_VOQ_ECC_ERR_ADDR_0_REG + j);
|
||||
p[420 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j);
|
||||
p[423 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j);
|
||||
p[426 + i] = dsaf_read_dev(ddev,
|
||||
p[424 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j);
|
||||
p[427 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j);
|
||||
p[430 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j);
|
||||
p[429 + i] = dsaf_read_dev(ddev,
|
||||
p[433 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j);
|
||||
p[432 + i] = dsaf_read_dev(ddev,
|
||||
p[436 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_VOQ_PPE_XOD_REQ_0_REG + j);
|
||||
p[435 + i] = dsaf_read_dev(ddev,
|
||||
p[439 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j);
|
||||
p[438 + i] = dsaf_read_dev(ddev,
|
||||
p[442 + i] = dsaf_read_dev(ddev,
|
||||
DSAF_VOQ_BP_ALL_THRD_0_REG + j);
|
||||
}
|
||||
|
||||
/* dsaf tbl registers */
|
||||
p[441] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG);
|
||||
p[442] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG);
|
||||
p[443] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG);
|
||||
p[444] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG);
|
||||
p[445] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG);
|
||||
p[446] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG);
|
||||
p[447] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG);
|
||||
p[448] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG);
|
||||
p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
|
||||
p[450] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG);
|
||||
p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG);
|
||||
p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG);
|
||||
p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG);
|
||||
p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
|
||||
p[455] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG);
|
||||
p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
|
||||
p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
|
||||
p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
|
||||
p[459] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
|
||||
p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
|
||||
p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
|
||||
p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
|
||||
p[463] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG);
|
||||
p[445] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG);
|
||||
p[446] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG);
|
||||
p[447] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG);
|
||||
p[448] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG);
|
||||
p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG);
|
||||
p[450] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG);
|
||||
p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG);
|
||||
p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG);
|
||||
p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
|
||||
p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG);
|
||||
p[455] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG);
|
||||
p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG);
|
||||
p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG);
|
||||
p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
|
||||
p[459] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG);
|
||||
p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
|
||||
p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
|
||||
p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
|
||||
p[463] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
|
||||
p[464] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
|
||||
p[465] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
|
||||
p[466] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
|
||||
p[467] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG);
|
||||
|
||||
for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
|
||||
j = i * 0x8;
|
||||
p[464 + 2 * i] = dsaf_read_dev(ddev,
|
||||
p[468 + 2 * i] = dsaf_read_dev(ddev,
|
||||
DSAF_TBL_DA0_MIS_INFO1_0_REG + j);
|
||||
p[465 + 2 * i] = dsaf_read_dev(ddev,
|
||||
p[469 + 2 * i] = dsaf_read_dev(ddev,
|
||||
DSAF_TBL_DA0_MIS_INFO0_0_REG + j);
|
||||
}
|
||||
|
||||
p[480] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG);
|
||||
p[481] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG);
|
||||
p[482] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG);
|
||||
p[483] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG);
|
||||
p[484] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG);
|
||||
p[485] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG);
|
||||
p[486] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG);
|
||||
p[487] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG);
|
||||
p[488] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG);
|
||||
p[489] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG);
|
||||
p[490] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG);
|
||||
p[491] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG);
|
||||
p[484] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG);
|
||||
p[485] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG);
|
||||
p[486] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG);
|
||||
p[487] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG);
|
||||
p[488] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG);
|
||||
p[489] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG);
|
||||
p[490] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG);
|
||||
p[491] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG);
|
||||
p[492] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG);
|
||||
p[493] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG);
|
||||
p[494] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG);
|
||||
p[495] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG);
|
||||
|
||||
/* dsaf other registers */
|
||||
p[492] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4);
|
||||
p[493] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4);
|
||||
p[494] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4);
|
||||
p[495] = dsaf_read_dev(ddev,
|
||||
p[496] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4);
|
||||
p[497] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4);
|
||||
p[498] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4);
|
||||
p[499] = dsaf_read_dev(ddev,
|
||||
DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4);
|
||||
p[496] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
|
||||
p[497] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
|
||||
p[500] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
|
||||
p[501] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
|
||||
|
||||
if (!is_ver1)
|
||||
p[498] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4);
|
||||
p[502] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4);
|
||||
|
||||
/* mark end of dsaf regs */
|
||||
for (i = 499; i < 504; i++)
|
||||
for (i = 503; i < 504; i++)
|
||||
p[i] = 0xdddddddd;
|
||||
}
|
||||
|
||||
|
|
|
@ -173,7 +173,7 @@
|
|||
#define DSAF_INODE_IN_DATA_STP_DISC_0_REG 0x1A50
|
||||
#define DSAF_INODE_GE_FC_EN_0_REG 0x1B00
|
||||
#define DSAF_INODE_VC0_IN_PKT_NUM_0_REG 0x1B50
|
||||
#define DSAF_INODE_VC1_IN_PKT_NUM_0_REG 0x1C00
|
||||
#define DSAF_INODE_VC1_IN_PKT_NUM_0_REG 0x103C
|
||||
#define DSAF_INODE_IN_PRIO_PAUSE_BASE_REG 0x1C00
|
||||
#define DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET 0x100
|
||||
#define DSAF_INODE_IN_PRIO_PAUSE_OFFSET 0x50
|
||||
|
@ -400,11 +400,11 @@
|
|||
#define RCB_ECC_ERR_ADDR4_REG 0x460
|
||||
#define RCB_ECC_ERR_ADDR5_REG 0x464
|
||||
|
||||
#define RCB_COM_SF_CFG_INTMASK_RING 0x480
|
||||
#define RCB_COM_SF_CFG_RING_STS 0x484
|
||||
#define RCB_COM_SF_CFG_RING 0x488
|
||||
#define RCB_COM_SF_CFG_INTMASK_BD 0x48C
|
||||
#define RCB_COM_SF_CFG_BD_RINT_STS 0x470
|
||||
#define RCB_COM_SF_CFG_INTMASK_RING 0x470
|
||||
#define RCB_COM_SF_CFG_RING_STS 0x474
|
||||
#define RCB_COM_SF_CFG_RING 0x478
|
||||
#define RCB_COM_SF_CFG_INTMASK_BD 0x47C
|
||||
#define RCB_COM_SF_CFG_BD_RINT_STS 0x480
|
||||
#define RCB_COM_RCB_RD_BD_BUSY 0x490
|
||||
#define RCB_COM_RCB_FBD_CRT_EN 0x494
|
||||
#define RCB_COM_AXI_WR_ERR_INTMASK 0x498
|
||||
|
@ -528,6 +528,7 @@
|
|||
#define GMAC_LD_LINK_COUNTER_REG 0x01D0UL
|
||||
#define GMAC_LOOP_REG 0x01DCUL
|
||||
#define GMAC_RECV_CONTROL_REG 0x01E0UL
|
||||
#define GMAC_PCS_RX_EN_REG 0x01E4UL
|
||||
#define GMAC_VLAN_CODE_REG 0x01E8UL
|
||||
#define GMAC_RX_OVERRUN_CNT_REG 0x01ECUL
|
||||
#define GMAC_RX_LENGTHFIELD_ERR_CNT_REG 0x01F4UL
|
||||
|
|
|
@ -1079,6 +1079,9 @@ int hns_nic_init_phy(struct net_device *ndev, struct hnae_handle *h)
|
|||
if (h->phy_if == PHY_INTERFACE_MODE_XGMII)
|
||||
phy_dev->autoneg = false;
|
||||
|
||||
if (h->phy_if == PHY_INTERFACE_MODE_SGMII)
|
||||
phy_stop(phy_dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -1192,6 +1195,22 @@ static void hns_set_irq_affinity(struct hns_nic_priv *priv)
|
|||
}
|
||||
}
|
||||
|
||||
static void hns_nic_free_irq(int q_num, struct hns_nic_priv *priv)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < q_num * 2; i++) {
|
||||
if (priv->ring_data[i].ring->irq_init_flag == RCB_IRQ_INITED) {
|
||||
irq_set_affinity_hint(priv->ring_data[i].ring->irq,
|
||||
NULL);
|
||||
free_irq(priv->ring_data[i].ring->irq,
|
||||
&priv->ring_data[i]);
|
||||
priv->ring_data[i].ring->irq_init_flag =
|
||||
RCB_IRQ_NOT_INITED;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int hns_nic_init_irq(struct hns_nic_priv *priv)
|
||||
{
|
||||
struct hnae_handle *h = priv->ae_handle;
|
||||
|
@ -1216,7 +1235,7 @@ static int hns_nic_init_irq(struct hns_nic_priv *priv)
|
|||
if (ret) {
|
||||
netdev_err(priv->netdev, "request irq(%d) fail\n",
|
||||
rd->ring->irq);
|
||||
return ret;
|
||||
goto out_free_irq;
|
||||
}
|
||||
disable_irq(rd->ring->irq);
|
||||
rd->ring->irq_init_flag = RCB_IRQ_INITED;
|
||||
|
@ -1226,6 +1245,10 @@ static int hns_nic_init_irq(struct hns_nic_priv *priv)
|
|||
hns_set_irq_affinity(priv);
|
||||
|
||||
return 0;
|
||||
|
||||
out_free_irq:
|
||||
hns_nic_free_irq(h->q_num, priv);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int hns_nic_net_up(struct net_device *ndev)
|
||||
|
@ -1235,6 +1258,9 @@ static int hns_nic_net_up(struct net_device *ndev)
|
|||
int i, j;
|
||||
int ret;
|
||||
|
||||
if (!test_bit(NIC_STATE_DOWN, &priv->state))
|
||||
return 0;
|
||||
|
||||
ret = hns_nic_init_irq(priv);
|
||||
if (ret != 0) {
|
||||
netdev_err(ndev, "hns init irq failed! ret=%d\n", ret);
|
||||
|
@ -1270,6 +1296,7 @@ out_has_some_queues:
|
|||
for (j = i - 1; j >= 0; j--)
|
||||
hns_nic_ring_close(ndev, j);
|
||||
|
||||
hns_nic_free_irq(h->q_num, priv);
|
||||
set_bit(NIC_STATE_DOWN, &priv->state);
|
||||
|
||||
return ret;
|
||||
|
@ -1380,12 +1407,20 @@ static int hns_nic_net_stop(struct net_device *ndev)
|
|||
}
|
||||
|
||||
static void hns_tx_timeout_reset(struct hns_nic_priv *priv);
|
||||
#define HNS_TX_TIMEO_LIMIT (40 * HZ)
|
||||
static void hns_nic_net_timeout(struct net_device *ndev)
|
||||
{
|
||||
struct hns_nic_priv *priv = netdev_priv(ndev);
|
||||
|
||||
if (ndev->watchdog_timeo < HNS_TX_TIMEO_LIMIT) {
|
||||
ndev->watchdog_timeo *= 2;
|
||||
netdev_info(ndev, "watchdog_timo changed to %d.\n",
|
||||
ndev->watchdog_timeo);
|
||||
} else {
|
||||
ndev->watchdog_timeo = HNS_NIC_TX_TIMEOUT;
|
||||
hns_tx_timeout_reset(priv);
|
||||
}
|
||||
}
|
||||
|
||||
static int hns_nic_do_ioctl(struct net_device *netdev, struct ifreq *ifr,
|
||||
int cmd)
|
||||
|
@ -1718,11 +1753,11 @@ static void hns_nic_service_task(struct work_struct *work)
|
|||
= container_of(work, struct hns_nic_priv, service_task);
|
||||
struct hnae_handle *h = priv->ae_handle;
|
||||
|
||||
hns_nic_reset_subtask(priv);
|
||||
hns_nic_update_link_status(priv->netdev);
|
||||
h->dev->ops->update_led_status(h);
|
||||
hns_nic_update_stats(priv->netdev);
|
||||
|
||||
hns_nic_reset_subtask(priv);
|
||||
hns_nic_service_event_complete(priv);
|
||||
}
|
||||
|
||||
|
@ -2001,7 +2036,7 @@ static int hns_nic_dev_probe(struct platform_device *pdev)
|
|||
|
||||
switch (priv->enet_ver) {
|
||||
case AE_VERSION_2:
|
||||
ndev->features |= NETIF_F_TSO | NETIF_F_TSO6;
|
||||
ndev->features |= NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_NTUPLE;
|
||||
ndev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
|
||||
NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
|
||||
NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6;
|
||||
|
|
|
@ -808,7 +808,7 @@ __vxge_hw_vpath_fw_ver_get(struct __vxge_hw_virtualpath *vpath,
|
|||
struct vxge_hw_device_date *fw_date = &hw_info->fw_date;
|
||||
struct vxge_hw_device_version *flash_version = &hw_info->flash_version;
|
||||
struct vxge_hw_device_date *flash_date = &hw_info->flash_date;
|
||||
u64 data0, data1 = 0, steer_ctrl = 0;
|
||||
u64 data0 = 0, data1 = 0, steer_ctrl = 0;
|
||||
enum vxge_hw_status status;
|
||||
|
||||
status = vxge_hw_vpath_fw_api(vpath,
|
||||
|
|
|
@ -918,7 +918,7 @@ static const struct net_device_ops w90p910_ether_netdev_ops = {
|
|||
.ndo_change_mtu = eth_change_mtu,
|
||||
};
|
||||
|
||||
static void __init get_mac_address(struct net_device *dev)
|
||||
static void get_mac_address(struct net_device *dev)
|
||||
{
|
||||
struct w90p910_ether *ether = netdev_priv(dev);
|
||||
struct platform_device *pdev;
|
||||
|
|
|
@ -1125,7 +1125,8 @@ netxen_validate_firmware(struct netxen_adapter *adapter)
|
|||
return -EINVAL;
|
||||
}
|
||||
val = nx_get_bios_version(adapter);
|
||||
netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
|
||||
if (netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios))
|
||||
return -EIO;
|
||||
if ((__force u32)val != bios) {
|
||||
dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
|
||||
fw_name[fw_type]);
|
||||
|
|
|
@ -2014,6 +2014,10 @@ static int lan78xx_set_mac_addr(struct net_device *netdev, void *p)
|
|||
ret = lan78xx_write_reg(dev, RX_ADDRL, addr_lo);
|
||||
ret = lan78xx_write_reg(dev, RX_ADDRH, addr_hi);
|
||||
|
||||
/* Added to support MAC address changes */
|
||||
ret = lan78xx_write_reg(dev, MAF_LO(0), addr_lo);
|
||||
ret = lan78xx_write_reg(dev, MAF_HI(0), addr_hi | MAF_HI_VALID_);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -616,7 +616,7 @@ struct b43_c32 b43_cordic(int theta)
|
|||
u8 i;
|
||||
s32 tmp;
|
||||
s8 signx = 1;
|
||||
u32 angle = 0;
|
||||
s32 angle = 0;
|
||||
struct b43_c32 ret = { .i = 39797, .q = 0, };
|
||||
|
||||
while (theta > (180 << 16))
|
||||
|
|
|
@ -274,7 +274,8 @@ static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
|
|||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
|
||||
|
||||
meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
|
||||
meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®,
|
||||
&bit);
|
||||
ret = regmap_update_bits(pc->reg_pullen, reg,
|
||||
BIT(bit), 0);
|
||||
if (ret)
|
||||
|
|
|
@ -427,14 +427,14 @@ static int olpc_bat_get_property(struct power_supply *psy,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
val->intval = (s16)be16_to_cpu(ec_word) * 100 / 256;
|
||||
val->intval = (s16)be16_to_cpu(ec_word) * 10 / 256;
|
||||
break;
|
||||
case POWER_SUPPLY_PROP_TEMP_AMBIENT:
|
||||
ret = olpc_ec_cmd(EC_AMB_TEMP, NULL, 0, (void *)&ec_word, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
val->intval = (int)be16_to_cpu(ec_word) * 100 / 256;
|
||||
val->intval = (int)be16_to_cpu(ec_word) * 10 / 256;
|
||||
break;
|
||||
case POWER_SUPPLY_PROP_CHARGE_COUNTER:
|
||||
ret = olpc_ec_cmd(EC_BAT_ACR, NULL, 0, (void *)&ec_word, 2);
|
||||
|
|
|
@ -275,16 +275,16 @@ static void zfcp_free_low_mem_buffers(struct zfcp_adapter *adapter)
|
|||
*/
|
||||
int zfcp_status_read_refill(struct zfcp_adapter *adapter)
|
||||
{
|
||||
while (atomic_read(&adapter->stat_miss) > 0)
|
||||
while (atomic_add_unless(&adapter->stat_miss, -1, 0))
|
||||
if (zfcp_fsf_status_read(adapter->qdio)) {
|
||||
atomic_inc(&adapter->stat_miss); /* undo add -1 */
|
||||
if (atomic_read(&adapter->stat_miss) >=
|
||||
adapter->stat_read_buf_num) {
|
||||
zfcp_erp_adapter_reopen(adapter, 0, "axsref1");
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
} else
|
||||
atomic_dec(&adapter->stat_miss);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -2331,7 +2331,7 @@ static int _bnx2fc_create(struct net_device *netdev,
|
|||
if (!interface) {
|
||||
printk(KERN_ERR PFX "bnx2fc_interface_create failed\n");
|
||||
rc = -ENOMEM;
|
||||
goto ifput_err;
|
||||
goto netdev_err;
|
||||
}
|
||||
|
||||
if (netdev->priv_flags & IFF_802_1Q_VLAN) {
|
||||
|
|
|
@ -631,8 +631,11 @@ static void cxgbit_send_halfclose(struct cxgbit_sock *csk)
|
|||
|
||||
static void cxgbit_arp_failure_discard(void *handle, struct sk_buff *skb)
|
||||
{
|
||||
struct cxgbit_sock *csk = handle;
|
||||
|
||||
pr_debug("%s cxgbit_device %p\n", __func__, handle);
|
||||
kfree_skb(skb);
|
||||
cxgbit_put_csk(csk);
|
||||
}
|
||||
|
||||
static void cxgbit_abort_arp_failure(void *handle, struct sk_buff *skb)
|
||||
|
@ -1136,7 +1139,7 @@ cxgbit_pass_accept_rpl(struct cxgbit_sock *csk, struct cpl_pass_accept_req *req)
|
|||
rpl5->opt0 = cpu_to_be64(opt0);
|
||||
rpl5->opt2 = cpu_to_be32(opt2);
|
||||
set_wr_txq(skb, CPL_PRIORITY_SETUP, csk->ctrlq_idx);
|
||||
t4_set_arp_err_handler(skb, NULL, cxgbit_arp_failure_discard);
|
||||
t4_set_arp_err_handler(skb, csk, cxgbit_arp_failure_discard);
|
||||
cxgbit_l2t_send(csk->com.cdev, skb, csk->l2t);
|
||||
}
|
||||
|
||||
|
|
|
@ -58,6 +58,7 @@ static void *cxgbit_uld_add(const struct cxgb4_lld_info *lldi)
|
|||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
kref_init(&cdev->kref);
|
||||
spin_lock_init(&cdev->np_lock);
|
||||
|
||||
cdev->lldi = *lldi;
|
||||
|
||||
|
|
|
@ -1393,22 +1393,43 @@ static inline struct console *SUNSU_CONSOLE(void)
|
|||
static enum su_type su_get_type(struct device_node *dp)
|
||||
{
|
||||
struct device_node *ap = of_find_node_by_path("/aliases");
|
||||
enum su_type rc = SU_PORT_PORT;
|
||||
|
||||
if (ap) {
|
||||
const char *keyb = of_get_property(ap, "keyboard", NULL);
|
||||
const char *ms = of_get_property(ap, "mouse", NULL);
|
||||
struct device_node *match;
|
||||
|
||||
if (keyb) {
|
||||
if (dp == of_find_node_by_path(keyb))
|
||||
return SU_PORT_KBD;
|
||||
match = of_find_node_by_path(keyb);
|
||||
|
||||
/*
|
||||
* The pointer is used as an identifier not
|
||||
* as a pointer, we can drop the refcount on
|
||||
* the of__node immediately after getting it.
|
||||
*/
|
||||
of_node_put(match);
|
||||
|
||||
if (dp == match) {
|
||||
rc = SU_PORT_KBD;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
if (ms) {
|
||||
if (dp == of_find_node_by_path(ms))
|
||||
return SU_PORT_MS;
|
||||
match = of_find_node_by_path(ms);
|
||||
|
||||
of_node_put(match);
|
||||
|
||||
if (dp == match) {
|
||||
rc = SU_PORT_MS;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return SU_PORT_PORT;
|
||||
out:
|
||||
of_node_put(ap);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int su_probe(struct platform_device *op)
|
||||
|
|
|
@ -520,6 +520,8 @@ static int vhost_vsock_dev_open(struct inode *inode, struct file *file)
|
|||
goto out;
|
||||
}
|
||||
|
||||
vsock->guest_cid = 0; /* no CID assigned yet */
|
||||
|
||||
atomic_set(&vsock->queued_replies, 0);
|
||||
|
||||
vqs[VSOCK_VQ_TX] = &vsock->vqs[VSOCK_VQ_TX];
|
||||
|
|
|
@ -3343,7 +3343,6 @@ retry:
|
|||
tcap->cap_id = t_cap_id;
|
||||
tcap->seq = t_seq - 1;
|
||||
tcap->issue_seq = t_seq - 1;
|
||||
tcap->mseq = t_mseq;
|
||||
tcap->issued |= issued;
|
||||
tcap->implemented |= issued;
|
||||
if (cap == ci->i_auth_cap)
|
||||
|
|
|
@ -1210,6 +1210,7 @@ static int create_lkb(struct dlm_ls *ls, struct dlm_lkb **lkb_ret)
|
|||
|
||||
if (rv < 0) {
|
||||
log_error(ls, "create_lkb idr error %d", rv);
|
||||
dlm_free_lkb(lkb);
|
||||
return rv;
|
||||
}
|
||||
|
||||
|
@ -4177,6 +4178,7 @@ static int receive_convert(struct dlm_ls *ls, struct dlm_message *ms)
|
|||
(unsigned long long)lkb->lkb_recover_seq,
|
||||
ms->m_header.h_nodeid, ms->m_lkid);
|
||||
error = -ENOENT;
|
||||
dlm_put_lkb(lkb);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
|
@ -4230,6 +4232,7 @@ static int receive_unlock(struct dlm_ls *ls, struct dlm_message *ms)
|
|||
lkb->lkb_id, lkb->lkb_remid,
|
||||
ms->m_header.h_nodeid, ms->m_lkid);
|
||||
error = -ENOENT;
|
||||
dlm_put_lkb(lkb);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
|
@ -5792,20 +5795,20 @@ int dlm_user_request(struct dlm_ls *ls, struct dlm_user_args *ua,
|
|||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
/* After ua is attached to lkb it will be freed by dlm_free_lkb().
|
||||
When DLM_IFL_USER is set, the dlm knows that this is a userspace
|
||||
lock and that lkb_astparam is the dlm_user_args structure. */
|
||||
|
||||
error = set_lock_args(mode, &ua->lksb, flags, namelen, timeout_cs,
|
||||
fake_astfn, ua, fake_bastfn, &args);
|
||||
lkb->lkb_flags |= DLM_IFL_USER;
|
||||
|
||||
if (error) {
|
||||
kfree(ua->lksb.sb_lvbptr);
|
||||
ua->lksb.sb_lvbptr = NULL;
|
||||
kfree(ua);
|
||||
__put_lkb(ls, lkb);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* After ua is attached to lkb it will be freed by dlm_free_lkb().
|
||||
When DLM_IFL_USER is set, the dlm knows that this is a userspace
|
||||
lock and that lkb_astparam is the dlm_user_args structure. */
|
||||
lkb->lkb_flags |= DLM_IFL_USER;
|
||||
error = request_lock(ls, lkb, name, namelen, &args);
|
||||
|
||||
switch (error) {
|
||||
|
|
|
@ -673,11 +673,11 @@ static int new_lockspace(const char *name, const char *cluster,
|
|||
kfree(ls->ls_recover_buf);
|
||||
out_lkbidr:
|
||||
idr_destroy(&ls->ls_lkbidr);
|
||||
out_rsbtbl:
|
||||
for (i = 0; i < DLM_REMOVE_NAMES_MAX; i++) {
|
||||
if (ls->ls_remove_names[i])
|
||||
kfree(ls->ls_remove_names[i]);
|
||||
}
|
||||
out_rsbtbl:
|
||||
vfree(ls->ls_rsbtbl);
|
||||
out_lsfree:
|
||||
if (do_unreg)
|
||||
|
|
|
@ -740,16 +740,18 @@ static int gfs2_create_inode(struct inode *dir, struct dentry *dentry,
|
|||
the gfs2 structures. */
|
||||
if (default_acl) {
|
||||
error = __gfs2_set_acl(inode, default_acl, ACL_TYPE_DEFAULT);
|
||||
posix_acl_release(default_acl);
|
||||
}
|
||||
if (acl) {
|
||||
if (!error)
|
||||
error = __gfs2_set_acl(inode, acl, ACL_TYPE_ACCESS);
|
||||
posix_acl_release(acl);
|
||||
}
|
||||
|
||||
if (error)
|
||||
goto fail_gunlock3;
|
||||
posix_acl_release(default_acl);
|
||||
default_acl = NULL;
|
||||
}
|
||||
if (acl) {
|
||||
error = __gfs2_set_acl(inode, acl, ACL_TYPE_ACCESS);
|
||||
if (error)
|
||||
goto fail_gunlock3;
|
||||
posix_acl_release(acl);
|
||||
acl = NULL;
|
||||
}
|
||||
|
||||
error = security_inode_init_security(&ip->i_inode, &dip->i_inode, name,
|
||||
&gfs2_initxattrs, NULL);
|
||||
|
@ -783,9 +785,7 @@ fail_free_inode:
|
|||
gfs2_glock_put(ip->i_gl);
|
||||
gfs2_rsqa_delete(ip, NULL);
|
||||
fail_free_acls:
|
||||
if (default_acl)
|
||||
posix_acl_release(default_acl);
|
||||
if (acl)
|
||||
posix_acl_release(acl);
|
||||
fail_gunlock:
|
||||
gfs2_dir_no_add(&da);
|
||||
|
|
|
@ -1705,9 +1705,9 @@ static int gfs2_rbm_find(struct gfs2_rbm *rbm, u8 state, u32 *minext,
|
|||
goto next_iter;
|
||||
}
|
||||
if (ret == -E2BIG) {
|
||||
n += rbm->bii - initial_bii;
|
||||
rbm->bii = 0;
|
||||
rbm->offset = 0;
|
||||
n += (rbm->bii - initial_bii);
|
||||
goto res_covered_end_of_rgrp;
|
||||
}
|
||||
return ret;
|
||||
|
|
|
@ -739,6 +739,15 @@
|
|||
|
||||
#define ABS_MISC 0x28
|
||||
|
||||
/*
|
||||
* 0x2e is reserved and should not be used in input drivers.
|
||||
* It was used by HID as ABS_MISC+6 and userspace needs to detect if
|
||||
* the next ABS_* event is correct or is just ABS_MISC + n.
|
||||
* We define here ABS_RESERVED so userspace can rely on it and detect
|
||||
* the situation described above.
|
||||
*/
|
||||
#define ABS_RESERVED 0x2e
|
||||
|
||||
#define ABS_MT_SLOT 0x2f /* MT slot being modified */
|
||||
#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */
|
||||
#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */
|
||||
|
|
|
@ -1611,8 +1611,6 @@ static __latent_entropy struct task_struct *copy_process(
|
|||
|
||||
posix_cpu_timers_init(p);
|
||||
|
||||
p->start_time = ktime_get_ns();
|
||||
p->real_start_time = ktime_get_boot_ns();
|
||||
p->io_context = NULL;
|
||||
p->audit_context = NULL;
|
||||
cgroup_fork(p);
|
||||
|
@ -1772,6 +1770,17 @@ static __latent_entropy struct task_struct *copy_process(
|
|||
if (retval)
|
||||
goto bad_fork_free_pid;
|
||||
|
||||
/*
|
||||
* From this point on we must avoid any synchronous user-space
|
||||
* communication until we take the tasklist-lock. In particular, we do
|
||||
* not want user-space to be able to predict the process start-time by
|
||||
* stalling fork(2) after we recorded the start_time but before it is
|
||||
* visible to the system.
|
||||
*/
|
||||
|
||||
p->start_time = ktime_get_ns();
|
||||
p->real_start_time = ktime_get_boot_ns();
|
||||
|
||||
/*
|
||||
* Make it visible to the rest of the system, but dont wake it up yet.
|
||||
* Need tasklist lock for parent etc handling!
|
||||
|
|
|
@ -305,15 +305,12 @@ void *devm_memremap_pages(struct device *dev, struct resource *res,
|
|||
is_ram = region_intersects(align_start, align_size,
|
||||
IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE);
|
||||
|
||||
if (is_ram == REGION_MIXED) {
|
||||
WARN_ONCE(1, "%s attempted on mixed region %pr\n",
|
||||
__func__, res);
|
||||
if (is_ram != REGION_DISJOINT) {
|
||||
WARN_ONCE(1, "%s attempted on %s region %pr\n", __func__,
|
||||
is_ram == REGION_MIXED ? "mixed" : "ram", res);
|
||||
return ERR_PTR(-ENXIO);
|
||||
}
|
||||
|
||||
if (is_ram == REGION_INTERSECTS)
|
||||
return __va(res->start);
|
||||
|
||||
if (!ref)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
|
@ -399,7 +396,7 @@ void *devm_memremap_pages(struct device *dev, struct resource *res,
|
|||
devres_free(page_map);
|
||||
return ERR_PTR(error);
|
||||
}
|
||||
EXPORT_SYMBOL(devm_memremap_pages);
|
||||
EXPORT_SYMBOL_GPL(devm_memremap_pages);
|
||||
|
||||
unsigned long vmem_altmap_offset(struct vmem_altmap *altmap)
|
||||
{
|
||||
|
|
|
@ -34,6 +34,7 @@
|
|||
#include <linux/memblock.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/compaction.h>
|
||||
#include <linux/rmap.h>
|
||||
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
|
@ -1617,6 +1618,21 @@ do_migrate_range(unsigned long start_pfn, unsigned long end_pfn)
|
|||
continue;
|
||||
}
|
||||
|
||||
/*
|
||||
* HWPoison pages have elevated reference counts so the migration would
|
||||
* fail on them. It also doesn't make any sense to migrate them in the
|
||||
* first place. Still try to unmap such a page in case it is still mapped
|
||||
* (e.g. current hwpoison implementation doesn't unmap KSM pages but keep
|
||||
* the unmap as the catch all safety net).
|
||||
*/
|
||||
if (PageHWPoison(page)) {
|
||||
if (WARN_ON(PageLRU(page)))
|
||||
isolate_lru_page(page);
|
||||
if (page_mapped(page))
|
||||
try_to_unmap(page, TTU_IGNORE_MLOCK | TTU_IGNORE_ACCESS);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!get_page_unless_zero(page))
|
||||
continue;
|
||||
/*
|
||||
|
|
|
@ -156,6 +156,12 @@ static int parse_opts(char *opts, struct p9_client *clnt)
|
|||
ret = r;
|
||||
continue;
|
||||
}
|
||||
if (option < 4096) {
|
||||
p9_debug(P9_DEBUG_ERROR,
|
||||
"msize should be at least 4k\n");
|
||||
ret = -EINVAL;
|
||||
continue;
|
||||
}
|
||||
clnt->msize = option;
|
||||
break;
|
||||
case Opt_trans:
|
||||
|
@ -972,10 +978,18 @@ static int p9_client_version(struct p9_client *c)
|
|||
else if (!strncmp(version, "9P2000", 6))
|
||||
c->proto_version = p9_proto_legacy;
|
||||
else {
|
||||
p9_debug(P9_DEBUG_ERROR,
|
||||
"server returned an unknown version: %s\n", version);
|
||||
err = -EREMOTEIO;
|
||||
goto error;
|
||||
}
|
||||
|
||||
if (msize < 4096) {
|
||||
p9_debug(P9_DEBUG_ERROR,
|
||||
"server returned a msize < 4096: %d\n", msize);
|
||||
err = -EREMOTEIO;
|
||||
goto error;
|
||||
}
|
||||
if (msize < c->msize)
|
||||
c->msize = msize;
|
||||
|
||||
|
@ -1040,6 +1054,13 @@ struct p9_client *p9_client_create(const char *dev_name, char *options)
|
|||
if (clnt->msize > clnt->trans_mod->maxsize)
|
||||
clnt->msize = clnt->trans_mod->maxsize;
|
||||
|
||||
if (clnt->msize < 4096) {
|
||||
p9_debug(P9_DEBUG_ERROR,
|
||||
"Please specify a msize of at least 4k\n");
|
||||
err = -EINVAL;
|
||||
goto free_client;
|
||||
}
|
||||
|
||||
err = p9_client_version(clnt);
|
||||
if (err)
|
||||
goto close_trans;
|
||||
|
|
|
@ -804,7 +804,7 @@ static int calc_signature(struct ceph_x_authorizer *au, struct ceph_msg *msg,
|
|||
void *enc_buf = au->enc_buf;
|
||||
int ret;
|
||||
|
||||
if (msg->con->peer_features & CEPH_FEATURE_CEPHX_V2) {
|
||||
if (!(msg->con->peer_features & CEPH_FEATURE_CEPHX_V2)) {
|
||||
struct {
|
||||
__le32 len;
|
||||
__le32 header_crc;
|
||||
|
|
|
@ -518,8 +518,8 @@ nla_put_failure:
|
|||
ret = -EMSGSIZE;
|
||||
} else {
|
||||
cb->args[IPSET_CB_ARG0] = i;
|
||||
}
|
||||
ipset_nest_end(skb, atd);
|
||||
}
|
||||
out:
|
||||
rcu_read_unlock();
|
||||
return ret;
|
||||
|
|
|
@ -115,12 +115,12 @@ static void nf_ct_sack_block_adjust(struct sk_buff *skb,
|
|||
/* TCP SACK sequence number adjustment */
|
||||
static unsigned int nf_ct_sack_adjust(struct sk_buff *skb,
|
||||
unsigned int protoff,
|
||||
struct tcphdr *tcph,
|
||||
struct nf_conn *ct,
|
||||
enum ip_conntrack_info ctinfo)
|
||||
{
|
||||
unsigned int dir, optoff, optend;
|
||||
struct tcphdr *tcph = (void *)skb->data + protoff;
|
||||
struct nf_conn_seqadj *seqadj = nfct_seqadj(ct);
|
||||
unsigned int dir, optoff, optend;
|
||||
|
||||
optoff = protoff + sizeof(struct tcphdr);
|
||||
optend = protoff + tcph->doff * 4;
|
||||
|
@ -128,6 +128,7 @@ static unsigned int nf_ct_sack_adjust(struct sk_buff *skb,
|
|||
if (!skb_make_writable(skb, optend))
|
||||
return 0;
|
||||
|
||||
tcph = (void *)skb->data + protoff;
|
||||
dir = CTINFO2DIR(ctinfo);
|
||||
|
||||
while (optoff < optend) {
|
||||
|
@ -207,7 +208,7 @@ int nf_ct_seq_adjust(struct sk_buff *skb,
|
|||
ntohl(newack));
|
||||
tcph->ack_seq = newack;
|
||||
|
||||
res = nf_ct_sack_adjust(skb, protoff, tcph, ct, ctinfo);
|
||||
res = nf_ct_sack_adjust(skb, protoff, ct, ctinfo);
|
||||
out:
|
||||
spin_unlock_bh(&ct->lock);
|
||||
|
||||
|
|
|
@ -1112,7 +1112,7 @@ static int svcauth_gss_legacy_init(struct svc_rqst *rqstp,
|
|||
struct kvec *resv = &rqstp->rq_res.head[0];
|
||||
struct rsi *rsip, rsikey;
|
||||
int ret;
|
||||
struct sunrpc_net *sn = net_generic(rqstp->rq_xprt->xpt_net, sunrpc_net_id);
|
||||
struct sunrpc_net *sn = net_generic(SVC_NET(rqstp), sunrpc_net_id);
|
||||
|
||||
memset(&rsikey, 0, sizeof(rsikey));
|
||||
ret = gss_read_verf(gc, argv, authp,
|
||||
|
@ -1223,7 +1223,7 @@ static int svcauth_gss_proxy_init(struct svc_rqst *rqstp,
|
|||
uint64_t handle;
|
||||
int status;
|
||||
int ret;
|
||||
struct net *net = rqstp->rq_xprt->xpt_net;
|
||||
struct net *net = SVC_NET(rqstp);
|
||||
struct sunrpc_net *sn = net_generic(net, sunrpc_net_id);
|
||||
|
||||
memset(&ud, 0, sizeof(ud));
|
||||
|
@ -1414,7 +1414,7 @@ svcauth_gss_accept(struct svc_rqst *rqstp, __be32 *authp)
|
|||
__be32 *rpcstart;
|
||||
__be32 *reject_stat = resv->iov_base + resv->iov_len;
|
||||
int ret;
|
||||
struct sunrpc_net *sn = net_generic(rqstp->rq_xprt->xpt_net, sunrpc_net_id);
|
||||
struct sunrpc_net *sn = net_generic(SVC_NET(rqstp), sunrpc_net_id);
|
||||
|
||||
dprintk("RPC: svcauth_gss: argv->iov_len = %zd\n",
|
||||
argv->iov_len);
|
||||
|
@ -1702,7 +1702,7 @@ svcauth_gss_release(struct svc_rqst *rqstp)
|
|||
struct rpc_gss_wire_cred *gc = &gsd->clcred;
|
||||
struct xdr_buf *resbuf = &rqstp->rq_res;
|
||||
int stat = -EINVAL;
|
||||
struct sunrpc_net *sn = net_generic(rqstp->rq_xprt->xpt_net, sunrpc_net_id);
|
||||
struct sunrpc_net *sn = net_generic(SVC_NET(rqstp), sunrpc_net_id);
|
||||
|
||||
if (gc->gc_proc != RPC_GSS_PROC_DATA)
|
||||
goto out;
|
||||
|
|
|
@ -54,6 +54,11 @@ static void cache_init(struct cache_head *h, struct cache_detail *detail)
|
|||
h->last_refresh = now;
|
||||
}
|
||||
|
||||
static void cache_fresh_locked(struct cache_head *head, time_t expiry,
|
||||
struct cache_detail *detail);
|
||||
static void cache_fresh_unlocked(struct cache_head *head,
|
||||
struct cache_detail *detail);
|
||||
|
||||
struct cache_head *sunrpc_cache_lookup(struct cache_detail *detail,
|
||||
struct cache_head *key, int hash)
|
||||
{
|
||||
|
@ -95,6 +100,7 @@ struct cache_head *sunrpc_cache_lookup(struct cache_detail *detail,
|
|||
if (cache_is_expired(detail, tmp)) {
|
||||
hlist_del_init(&tmp->cache_list);
|
||||
detail->entries --;
|
||||
cache_fresh_locked(tmp, 0, detail);
|
||||
freeme = tmp;
|
||||
break;
|
||||
}
|
||||
|
@ -110,8 +116,10 @@ struct cache_head *sunrpc_cache_lookup(struct cache_detail *detail,
|
|||
cache_get(new);
|
||||
write_unlock(&detail->hash_lock);
|
||||
|
||||
if (freeme)
|
||||
if (freeme) {
|
||||
cache_fresh_unlocked(freeme, detail);
|
||||
cache_put(freeme, detail);
|
||||
}
|
||||
return new;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sunrpc_cache_lookup);
|
||||
|
|
|
@ -2209,8 +2209,8 @@ static void xs_udp_setup_socket(struct work_struct *work)
|
|||
trace_rpc_socket_connect(xprt, sock, 0);
|
||||
status = 0;
|
||||
out:
|
||||
xprt_unlock_connect(xprt, transport);
|
||||
xprt_clear_connecting(xprt);
|
||||
xprt_unlock_connect(xprt, transport);
|
||||
xprt_wake_pending_tasks(xprt, status);
|
||||
}
|
||||
|
||||
|
@ -2395,8 +2395,8 @@ static void xs_tcp_setup_socket(struct work_struct *work)
|
|||
}
|
||||
status = -EAGAIN;
|
||||
out:
|
||||
xprt_unlock_connect(xprt, transport);
|
||||
xprt_clear_connecting(xprt);
|
||||
xprt_unlock_connect(xprt, transport);
|
||||
xprt_wake_pending_tasks(xprt, status);
|
||||
}
|
||||
|
||||
|
|
|
@ -641,7 +641,7 @@ void xfrm_sad_getinfo(struct net *net, struct xfrmk_sadinfo *si)
|
|||
{
|
||||
spin_lock_bh(&net->xfrm.xfrm_state_lock);
|
||||
si->sadcnt = net->xfrm.state_num;
|
||||
si->sadhcnt = net->xfrm.state_hmask;
|
||||
si->sadhcnt = net->xfrm.state_hmask + 1;
|
||||
si->sadhmcnt = xfrm_state_hashmax;
|
||||
spin_unlock_bh(&net->xfrm.xfrm_state_lock);
|
||||
}
|
||||
|
|
|
@ -899,6 +899,9 @@ int cs46xx_dsp_proc_done (struct snd_cs46xx *chip)
|
|||
struct dsp_spos_instance * ins = chip->dsp_spos_instance;
|
||||
int i;
|
||||
|
||||
if (!ins)
|
||||
return 0;
|
||||
|
||||
snd_info_free_entry(ins->proc_sym_info_entry);
|
||||
ins->proc_sym_info_entry = NULL;
|
||||
|
||||
|
|
|
@ -1882,7 +1882,7 @@ static int build_audio_procunit(struct mixer_build *state, int unitid,
|
|||
char *name)
|
||||
{
|
||||
struct uac_processing_unit_descriptor *desc = raw_desc;
|
||||
int num_ins = desc->bNrInPins;
|
||||
int num_ins;
|
||||
struct usb_mixer_elem_info *cval;
|
||||
struct snd_kcontrol *kctl;
|
||||
int i, err, nameid, type, len;
|
||||
|
@ -1897,7 +1897,13 @@ static int build_audio_procunit(struct mixer_build *state, int unitid,
|
|||
0, NULL, default_value_info
|
||||
};
|
||||
|
||||
if (desc->bLength < 13 || desc->bLength < 13 + num_ins ||
|
||||
if (desc->bLength < 13) {
|
||||
usb_audio_err(state->chip, "invalid %s descriptor (id %d)\n", name, unitid);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
num_ins = desc->bNrInPins;
|
||||
if (desc->bLength < 13 + num_ins ||
|
||||
desc->bLength < num_ins + uac_processing_unit_bControlSize(desc, state->mixer->protocol)) {
|
||||
usb_audio_err(state->chip, "invalid %s descriptor (id %d)\n", name, unitid);
|
||||
return -EINVAL;
|
||||
|
|
|
@ -3321,6 +3321,9 @@ AU0828_DEVICE(0x2040, 0x7270, "Hauppauge", "HVR-950Q"),
|
|||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
.ifnum = -1
|
||||
},
|
||||
}
|
||||
}
|
||||
},
|
||||
|
|
|
@ -114,7 +114,7 @@ void *__wrap_devm_memremap_pages(struct device *dev, struct resource *res,
|
|||
return nfit_res->buf + offset - nfit_res->res.start;
|
||||
return devm_memremap_pages(dev, res, ref, altmap);
|
||||
}
|
||||
EXPORT_SYMBOL(__wrap_devm_memremap_pages);
|
||||
EXPORT_SYMBOL_GPL(__wrap_devm_memremap_pages);
|
||||
|
||||
pfn_t __wrap_phys_to_pfn_t(phys_addr_t addr, unsigned long flags)
|
||||
{
|
||||
|
|
Loading…
Reference in New Issue