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lineage_android_kernel_xiaomi_sdm845
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Merge branch 'renesas-sh7372' into renesas-soc 

* renesas-sh7372:
  ARM: shmobile: Fix build problem in pm-sh7372.c for unusual .config
  ARM: shmobile: Take cpuidle dependencies into account correctly
  ARM: shmobile: sh7372: completely switch over to using pm-rmobile API
  ARM: shmobile: ap4evb: switch to using pm-rmobile API
  ARM: shmobile: mackerel: switch to using pm-rmobile API
  ARM: shmobile: sh7372: add pm-rmobile domain support
  ARM: shmobile: sh7372 A3SM CPUIdle support
  ARM: shmobile: Use INTCA with sh7372 A3SM power domain
  ARM: shmobile: use common DMAEngine definitions on sh7372
  ARM: shmobile: sh7372: remove unused sh7372_a3sp_init() on !CONFIG_PM
This commit is contained in:
Rafael J. Wysocki 2012-07-11 23:02:31 +02:00
parent 0b14121f93 911a472aca
commit 27748df5ee
6 changed files with 206 additions and 392 deletions
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1
arch/arm/mach-shmobile/Kconfig
View File

@ -19,6 +19,7 @@ config ARCH_SH7372
select CPU_V7 select CPU_V7
select SH_CLK_CPG select SH_CLK_CPG
select ARCH_WANT_OPTIONAL_GPIOLIB select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_CPU_SUSPEND if PM || CPU_IDLE
config ARCH_SH73A0 config ARCH_SH73A0
bool "SH-Mobile AG5 (R8A73A00)" bool "SH-Mobile AG5 (R8A73A00)"

14
arch/arm/mach-shmobile/board-ap4evb.c
View File

@ -1447,14 +1447,14 @@ static void __init ap4evb_init(void)
platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc1_device); rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc1_device);
sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device); rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device); rmobile_add_device_to_domain(&sh7372_pd_a4mp, &fsi_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sh_mmcif_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi1_device);
sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device); rmobile_add_device_to_domain(&sh7372_pd_a4r, &ceu_device);
hdmi_init_pm_clock(); hdmi_init_pm_clock();
fsi_init_pm_clock(); fsi_init_pm_clock();

24
arch/arm/mach-shmobile/board-mackerel.c
View File

@ -1614,20 +1614,20 @@ static void __init mackerel_init(void)
platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices)); platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device); rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4lc, &hdmi_lcdc_device); rmobile_add_device_to_domain(&sh7372_pd_a4lc, &hdmi_lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4lc, &meram_device); rmobile_add_device_to_domain(&sh7372_pd_a4lc, &meram_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device); rmobile_add_device_to_domain(&sh7372_pd_a4mp, &fsi_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs0_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usbhs0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs1_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usbhs1_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &nand_flash_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &nand_flash_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sh_mmcif_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi0_device);
#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi1_device);
#endif #endif
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi2_device);
sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device); rmobile_add_device_to_domain(&sh7372_pd_a4r, &ceu_device);
hdmi_init_pm_clock(); hdmi_init_pm_clock();
sh7372_pm_init(); sh7372_pm_init();

45
arch/arm/mach-shmobile/include/mach/sh7372.h
View File

@ -13,6 +13,7 @@
#include <linux/sh_clk.h> #include <linux/sh_clk.h>
#include <linux/pm_domain.h> #include <linux/pm_domain.h>
#include <mach/pm-rmobile.h>
/* /*
* Pin Function Controller: * Pin Function Controller:
@ -477,42 +478,16 @@ extern struct clk sh7372_fsibck_clk;
extern struct clk sh7372_fsidiva_clk; extern struct clk sh7372_fsidiva_clk;
extern struct clk sh7372_fsidivb_clk; extern struct clk sh7372_fsidivb_clk;
struct platform_device;
struct sh7372_pm_domain {
struct generic_pm_domain genpd;
struct dev_power_governor *gov;
int (*suspend)(void);
void (*resume)(void);
unsigned int bit_shift;
bool no_debug;
};
static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d)
{
return container_of(d, struct sh7372_pm_domain, genpd);
}
#ifdef CONFIG_PM #ifdef CONFIG_PM
extern struct sh7372_pm_domain sh7372_a4lc; extern struct rmobile_pm_domain sh7372_pd_a4lc;
extern struct sh7372_pm_domain sh7372_a4mp; extern struct rmobile_pm_domain sh7372_pd_a4mp;
extern struct sh7372_pm_domain sh7372_d4; extern struct rmobile_pm_domain sh7372_pd_d4;
extern struct sh7372_pm_domain sh7372_a4r; extern struct rmobile_pm_domain sh7372_pd_a4r;
extern struct sh7372_pm_domain sh7372_a3rv; extern struct rmobile_pm_domain sh7372_pd_a3rv;
extern struct sh7372_pm_domain sh7372_a3ri; extern struct rmobile_pm_domain sh7372_pd_a3ri;
extern struct sh7372_pm_domain sh7372_a4s; extern struct rmobile_pm_domain sh7372_pd_a4s;
extern struct sh7372_pm_domain sh7372_a3sp; extern struct rmobile_pm_domain sh7372_pd_a3sp;
extern struct sh7372_pm_domain sh7372_a3sg; extern struct rmobile_pm_domain sh7372_pd_a3sg;
extern void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd);
extern void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
struct platform_device *pdev);
extern void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
struct sh7372_pm_domain *sh7372_sd);
#else
#define sh7372_init_pm_domain(pd) do { } while(0)
#define sh7372_add_device_to_domain(pd, pdev) do { } while(0)
#define sh7372_pm_add_subdomain(pd, sd) do { } while(0)
#endif /* CONFIG_PM */ #endif /* CONFIG_PM */
extern void sh7372_intcs_suspend(void); extern void sh7372_intcs_suspend(void);

309
arch/arm/mach-shmobile/pm-sh7372.c
View File

@ -26,6 +26,7 @@
#include <asm/suspend.h> #include <asm/suspend.h>
#include <mach/common.h> #include <mach/common.h>
#include <mach/sh7372.h> #include <mach/sh7372.h>
#include <mach/pm-rmobile.h>
/* DBG */ /* DBG */
#define DBGREG1 0xe6100020 #define DBGREG1 0xe6100020
@ -41,13 +42,10 @@
#define PLLC01STPCR 0xe61500c8 #define PLLC01STPCR 0xe61500c8
/* SYSC */ /* SYSC */
#define SPDCR 0xe6180008
#define SWUCR 0xe6180014
#define SBAR 0xe6180020 #define SBAR 0xe6180020
#define WUPRMSK 0xe6180028 #define WUPRMSK 0xe6180028
#define WUPSMSK 0xe618002c #define WUPSMSK 0xe618002c
#define WUPSMSK2 0xe6180048 #define WUPSMSK2 0xe6180048
#define PSTR 0xe6180080
#define WUPSFAC 0xe6180098 #define WUPSFAC 0xe6180098
#define IRQCR 0xe618022c #define IRQCR 0xe618022c
#define IRQCR2 0xe6180238 #define IRQCR2 0xe6180238
@ -71,188 +69,48 @@
/* AP-System Core */ /* AP-System Core */
#define APARMBAREA 0xe6f10020 #define APARMBAREA 0xe6f10020
#define PSTR_RETRIES 100
#define PSTR_DELAY_US 10
#ifdef CONFIG_PM #ifdef CONFIG_PM
static int pd_power_down(struct generic_pm_domain *genpd) struct rmobile_pm_domain sh7372_pd_a4lc = {
{ .genpd.name = "A4LC",
struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd); .bit_shift = 1,
unsigned int mask = 1 << sh7372_pd->bit_shift; };
if (sh7372_pd->suspend) { struct rmobile_pm_domain sh7372_pd_a4mp = {
int ret = sh7372_pd->suspend(); .genpd.name = "A4MP",
.bit_shift = 2,
};
if (ret) struct rmobile_pm_domain sh7372_pd_d4 = {
return ret; .genpd.name = "D4",
} .bit_shift = 3,
};
if (__raw_readl(PSTR) & mask) { static int sh7372_a4r_pd_suspend(void)
unsigned int retry_count;
__raw_writel(mask, SPDCR);
for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
if (!(__raw_readl(SPDCR) & mask))
break;
cpu_relax();
}
}
if (!sh7372_pd->no_debug)
pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n",
genpd->name, mask, __raw_readl(PSTR));
return 0;
}
static int __pd_power_up(struct sh7372_pm_domain *sh7372_pd, bool do_resume)
{
unsigned int mask = 1 << sh7372_pd->bit_shift;
unsigned int retry_count;
int ret = 0;
if (__raw_readl(PSTR) & mask)
goto out;
__raw_writel(mask, SWUCR);
for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
if (!(__raw_readl(SWUCR) & mask))
break;
if (retry_count > PSTR_RETRIES)
udelay(PSTR_DELAY_US);
else
cpu_relax();
}
if (!retry_count)
ret = -EIO;
if (!sh7372_pd->no_debug)
pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
sh7372_pd->genpd.name, mask, __raw_readl(PSTR));
out:
if (ret == 0 && sh7372_pd->resume && do_resume)
sh7372_pd->resume();
return ret;
}
static int pd_power_up(struct generic_pm_domain *genpd)
{
return __pd_power_up(to_sh7372_pd(genpd), true);
}
static int sh7372_a4r_suspend(void)
{ {
sh7372_intcs_suspend(); sh7372_intcs_suspend();
__raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */ __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
return 0; return 0;
} }
static bool pd_active_wakeup(struct device *dev) struct rmobile_pm_domain sh7372_pd_a4r = {
{
bool (*active_wakeup)(struct device *dev);
active_wakeup = dev_gpd_data(dev)->ops.active_wakeup;
return active_wakeup ? active_wakeup(dev) : true;
}
static int sh7372_stop_dev(struct device *dev)
{
int (*stop)(struct device *dev);
stop = dev_gpd_data(dev)->ops.stop;
if (stop) {
int ret = stop(dev);
if (ret)
return ret;
}
return pm_clk_suspend(dev);
}
static int sh7372_start_dev(struct device *dev)
{
int (*start)(struct device *dev);
int ret;
ret = pm_clk_resume(dev);
if (ret)
return ret;
start = dev_gpd_data(dev)->ops.start;
if (start)
ret = start(dev);
return ret;
}
void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
{
struct generic_pm_domain *genpd = &sh7372_pd->genpd;
struct dev_power_governor *gov = sh7372_pd->gov;
pm_genpd_init(genpd, gov ? : &simple_qos_governor, false);
genpd->dev_ops.stop = sh7372_stop_dev;
genpd->dev_ops.start = sh7372_start_dev;
genpd->dev_ops.active_wakeup = pd_active_wakeup;
genpd->dev_irq_safe = true;
genpd->power_off = pd_power_down;
genpd->power_on = pd_power_up;
__pd_power_up(sh7372_pd, false);
}
void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
pm_genpd_add_device(&sh7372_pd->genpd, dev);
if (pm_clk_no_clocks(dev))
pm_clk_add(dev, NULL);
}
void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
struct sh7372_pm_domain *sh7372_sd)
{
pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd);
}
struct sh7372_pm_domain sh7372_a4lc = {
.genpd.name = "A4LC",
.bit_shift = 1,
};
struct sh7372_pm_domain sh7372_a4mp = {
.genpd.name = "A4MP",
.bit_shift = 2,
};
struct sh7372_pm_domain sh7372_d4 = {
.genpd.name = "D4",
.bit_shift = 3,
};
struct sh7372_pm_domain sh7372_a4r = {
.genpd.name = "A4R", .genpd.name = "A4R",
.bit_shift = 5, .bit_shift = 5,
.suspend = sh7372_a4r_suspend, .suspend = sh7372_a4r_pd_suspend,
.resume = sh7372_intcs_resume, .resume = sh7372_intcs_resume,
}; };
struct sh7372_pm_domain sh7372_a3rv = { struct rmobile_pm_domain sh7372_pd_a3rv = {
.genpd.name = "A3RV", .genpd.name = "A3RV",
.bit_shift = 6, .bit_shift = 6,
}; };
struct sh7372_pm_domain sh7372_a3ri = { struct rmobile_pm_domain sh7372_pd_a3ri = {
.genpd.name = "A3RI", .genpd.name = "A3RI",
.bit_shift = 8, .bit_shift = 8,
}; };
static int sh7372_a4s_suspend(void) static int sh7372_pd_a4s_suspend(void)
{ {
/* /*
* The A4S domain contains the CPU core and therefore it should * The A4S domain contains the CPU core and therefore it should
@ -261,15 +119,15 @@ static int sh7372_a4s_suspend(void)
return -EBUSY; return -EBUSY;
} }
struct sh7372_pm_domain sh7372_a4s = { struct rmobile_pm_domain sh7372_pd_a4s = {
.genpd.name = "A4S", .genpd.name = "A4S",
.bit_shift = 10, .bit_shift = 10,
.gov = &pm_domain_always_on_gov, .gov = &pm_domain_always_on_gov,
.no_debug = true, .no_debug = true,
.suspend = sh7372_a4s_suspend, .suspend = sh7372_pd_a4s_suspend,
}; };
static int sh7372_a3sp_suspend(void) static int sh7372_a3sp_pd_suspend(void)
{ {
/* /*
* Serial consoles make use of SCIF hardware located in A3SP, * Serial consoles make use of SCIF hardware located in A3SP,
@ -278,32 +136,22 @@ static int sh7372_a3sp_suspend(void)
return console_suspend_enabled ? 0 : -EBUSY; return console_suspend_enabled ? 0 : -EBUSY;
} }
struct sh7372_pm_domain sh7372_a3sp = { struct rmobile_pm_domain sh7372_pd_a3sp = {
.genpd.name = "A3SP", .genpd.name = "A3SP",
.bit_shift = 11, .bit_shift = 11,
.gov = &pm_domain_always_on_gov, .gov = &pm_domain_always_on_gov,
.no_debug = true, .no_debug = true,
.suspend = sh7372_a3sp_suspend, .suspend = sh7372_a3sp_pd_suspend,
}; };
struct sh7372_pm_domain sh7372_a3sg = { struct rmobile_pm_domain sh7372_pd_a3sg = {
.genpd.name = "A3SG", .genpd.name = "A3SG",
.bit_shift = 13, .bit_shift = 13,
}; };
#else /* !CONFIG_PM */ #endif /* CONFIG_PM */
static inline void sh7372_a3sp_init(void) {}
#endif /* !CONFIG_PM */
#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
static int sh7372_do_idle_core_standby(unsigned long unused)
{
cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
return 0;
}
static void sh7372_set_reset_vector(unsigned long address) static void sh7372_set_reset_vector(unsigned long address)
{ {
/* set reset vector, translate 4k */ /* set reset vector, translate 4k */
@ -311,21 +159,6 @@ static void sh7372_set_reset_vector(unsigned long address)
__raw_writel(0, APARMBAREA); __raw_writel(0, APARMBAREA);
} }
static void sh7372_enter_core_standby(void)
{
sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
/* enter sleep mode with SYSTBCR to 0x10 */
__raw_writel(0x10, SYSTBCR);
cpu_suspend(0, sh7372_do_idle_core_standby);
__raw_writel(0, SYSTBCR);
/* disable reset vector translation */
__raw_writel(0, SBAR);
}
#endif
#ifdef CONFIG_SUSPEND
static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode) static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode)
{ {
if (pllc0_on) if (pllc0_on)
@ -465,22 +298,42 @@ static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2)
static void sh7372_enter_a3sm_common(int pllc0_on) static void sh7372_enter_a3sm_common(int pllc0_on)
{ {
/* use INTCA together with SYSC for wakeup */
sh7372_setup_sysc(1 << 0, 0);
sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc)); sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
sh7372_enter_sysc(pllc0_on, 1 << 12); sh7372_enter_sysc(pllc0_on, 1 << 12);
} }
#endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */
static void sh7372_enter_a4s_common(int pllc0_on)
{
sh7372_intca_suspend();
memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
sh7372_set_reset_vector(SMFRAM);
sh7372_enter_sysc(pllc0_on, 1 << 10);
sh7372_intca_resume();
}
#endif
#ifdef CONFIG_CPU_IDLE #ifdef CONFIG_CPU_IDLE
static int sh7372_do_idle_core_standby(unsigned long unused)
{
cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
return 0;
}
static void sh7372_enter_core_standby(void)
{
sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
/* enter sleep mode with SYSTBCR to 0x10 */
__raw_writel(0x10, SYSTBCR);
cpu_suspend(0, sh7372_do_idle_core_standby);
__raw_writel(0, SYSTBCR);
/* disable reset vector translation */
__raw_writel(0, SBAR);
}
static void sh7372_enter_a3sm_pll_on(void)
{
sh7372_enter_a3sm_common(1);
}
static void sh7372_enter_a3sm_pll_off(void)
{
sh7372_enter_a3sm_common(0);
}
static void sh7372_cpuidle_setup(struct cpuidle_driver *drv) static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
{ {
@ -492,7 +345,24 @@ static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
state->target_residency = 20 + 10; state->target_residency = 20 + 10;
state->flags = CPUIDLE_FLAG_TIME_VALID; state->flags = CPUIDLE_FLAG_TIME_VALID;
shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby; shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby;
drv->state_count++;
state = &drv->states[drv->state_count];
snprintf(state->name, CPUIDLE_NAME_LEN, "C3");
strncpy(state->desc, "A3SM PLL ON", CPUIDLE_DESC_LEN);
state->exit_latency = 20;
state->target_residency = 30 + 20;
state->flags = CPUIDLE_FLAG_TIME_VALID;
shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_on;
drv->state_count++;
state = &drv->states[drv->state_count];
snprintf(state->name, CPUIDLE_NAME_LEN, "C4");
strncpy(state->desc, "A3SM PLL OFF", CPUIDLE_DESC_LEN);
state->exit_latency = 120;
state->target_residency = 30 + 120;
state->flags = CPUIDLE_FLAG_TIME_VALID;
shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_off;
drv->state_count++; drv->state_count++;
} }
@ -505,6 +375,14 @@ static void sh7372_cpuidle_init(void) {}
#endif #endif
#ifdef CONFIG_SUSPEND #ifdef CONFIG_SUSPEND
static void sh7372_enter_a4s_common(int pllc0_on)
{
sh7372_intca_suspend();
memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
sh7372_set_reset_vector(SMFRAM);
sh7372_enter_sysc(pllc0_on, 1 << 10);
sh7372_intca_resume();
}
static int sh7372_enter_suspend(suspend_state_t suspend_state) static int sh7372_enter_suspend(suspend_state_t suspend_state)
{ {
@ -512,24 +390,21 @@ static int sh7372_enter_suspend(suspend_state_t suspend_state)
/* check active clocks to determine potential wakeup sources */ /* check active clocks to determine potential wakeup sources */
if (sh7372_sysc_valid(&msk, &msk2)) { if (sh7372_sysc_valid(&msk, &msk2)) {
/* convert INTC mask and sense to SYSC mask and sense */
sh7372_setup_sysc(msk, msk2);
if (!console_suspend_enabled && if (!console_suspend_enabled &&
sh7372_a4s.genpd.status == GPD_STATE_POWER_OFF) { sh7372_pd_a4s.genpd.status == GPD_STATE_POWER_OFF) {
/* convert INTC mask/sense to SYSC mask/sense */
sh7372_setup_sysc(msk, msk2);
/* enter A4S sleep with PLLC0 off */ /* enter A4S sleep with PLLC0 off */
pr_debug("entering A4S\n"); pr_debug("entering A4S\n");
sh7372_enter_a4s_common(0); sh7372_enter_a4s_common(0);
} else { return 0;
/* enter A3SM sleep with PLLC0 off */
pr_debug("entering A3SM\n");
sh7372_enter_a3sm_common(0);
} }
} else {
/* default to Core Standby that supports all wakeup sources */
pr_debug("entering Core Standby\n");
sh7372_enter_core_standby();
} }
/* default to enter A3SM sleep with PLLC0 off */
pr_debug("entering A3SM\n");
sh7372_enter_a3sm_common(0);
return 0; return 0;
} }
@ -550,7 +425,7 @@ static int sh7372_pm_notifier_fn(struct notifier_block *notifier,
* executed during system suspend and resume, respectively, so * executed during system suspend and resume, respectively, so
* that those functions don't crash while accessing the INTCS. * that those functions don't crash while accessing the INTCS.
*/ */
pm_genpd_poweron(&sh7372_a4r.genpd); pm_genpd_poweron(&sh7372_pd_a4r.genpd);
break; break;
case PM_POST_SUSPEND: case PM_POST_SUSPEND:
pm_genpd_poweroff_unused(); pm_genpd_poweroff_unused();

205
arch/arm/mach-shmobile/setup-sh7372.c
View File

@ -33,6 +33,7 @@
#include <linux/sh_timer.h> #include <linux/sh_timer.h>
#include <linux/pm_domain.h> #include <linux/pm_domain.h>
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
#include <mach/dma-register.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/irqs.h> #include <mach/irqs.h>
#include <mach/sh7372.h> #include <mach/sh7372.h>
@ -335,151 +336,126 @@ static struct platform_device iic1_device = {
}; };
/* DMA */ /* DMA */
/* Transmit sizes and respective CHCR register values */
enum {
XMIT_SZ_8BIT = 0,
XMIT_SZ_16BIT = 1,
XMIT_SZ_32BIT = 2,
XMIT_SZ_64BIT = 7,
XMIT_SZ_128BIT = 3,
XMIT_SZ_256BIT = 4,
XMIT_SZ_512BIT = 5,
};
/* log2(size / 8) - used to calculate number of transfers */
#define TS_SHIFT { \
[XMIT_SZ_8BIT] = 0, \
[XMIT_SZ_16BIT] = 1, \
[XMIT_SZ_32BIT] = 2, \
[XMIT_SZ_64BIT] = 3, \
[XMIT_SZ_128BIT] = 4, \
[XMIT_SZ_256BIT] = 5, \
[XMIT_SZ_512BIT] = 6, \
}
#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
(((i) & 0xc) << (20 - 2)))
static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = { static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
{ {
.slave_id = SHDMA_SLAVE_SCIF0_TX, .slave_id = SHDMA_SLAVE_SCIF0_TX,
.addr = 0xe6c40020, .addr = 0xe6c40020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x21, .mid_rid = 0x21,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF0_RX, .slave_id = SHDMA_SLAVE_SCIF0_RX,
.addr = 0xe6c40024, .addr = 0xe6c40024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x22, .mid_rid = 0x22,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF1_TX, .slave_id = SHDMA_SLAVE_SCIF1_TX,
.addr = 0xe6c50020, .addr = 0xe6c50020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x25, .mid_rid = 0x25,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF1_RX, .slave_id = SHDMA_SLAVE_SCIF1_RX,
.addr = 0xe6c50024, .addr = 0xe6c50024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x26, .mid_rid = 0x26,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF2_TX, .slave_id = SHDMA_SLAVE_SCIF2_TX,
.addr = 0xe6c60020, .addr = 0xe6c60020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x29, .mid_rid = 0x29,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF2_RX, .slave_id = SHDMA_SLAVE_SCIF2_RX,
.addr = 0xe6c60024, .addr = 0xe6c60024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x2a, .mid_rid = 0x2a,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF3_TX, .slave_id = SHDMA_SLAVE_SCIF3_TX,
.addr = 0xe6c70020, .addr = 0xe6c70020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x2d, .mid_rid = 0x2d,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF3_RX, .slave_id = SHDMA_SLAVE_SCIF3_RX,
.addr = 0xe6c70024, .addr = 0xe6c70024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x2e, .mid_rid = 0x2e,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF4_TX, .slave_id = SHDMA_SLAVE_SCIF4_TX,
.addr = 0xe6c80020, .addr = 0xe6c80020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x39, .mid_rid = 0x39,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF4_RX, .slave_id = SHDMA_SLAVE_SCIF4_RX,
.addr = 0xe6c80024, .addr = 0xe6c80024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x3a, .mid_rid = 0x3a,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF5_TX, .slave_id = SHDMA_SLAVE_SCIF5_TX,
.addr = 0xe6cb0020, .addr = 0xe6cb0020,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x35, .mid_rid = 0x35,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF5_RX, .slave_id = SHDMA_SLAVE_SCIF5_RX,
.addr = 0xe6cb0024, .addr = 0xe6cb0024,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x36, .mid_rid = 0x36,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF6_TX, .slave_id = SHDMA_SLAVE_SCIF6_TX,
.addr = 0xe6c30040, .addr = 0xe6c30040,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x3d, .mid_rid = 0x3d,
}, { }, {
.slave_id = SHDMA_SLAVE_SCIF6_RX, .slave_id = SHDMA_SLAVE_SCIF6_RX,
.addr = 0xe6c30060, .addr = 0xe6c30060,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x3e, .mid_rid = 0x3e,
}, { }, {
.slave_id = SHDMA_SLAVE_SDHI0_TX, .slave_id = SHDMA_SLAVE_SDHI0_TX,
.addr = 0xe6850030, .addr = 0xe6850030,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), .chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xc1, .mid_rid = 0xc1,
}, { }, {
.slave_id = SHDMA_SLAVE_SDHI0_RX, .slave_id = SHDMA_SLAVE_SDHI0_RX,
.addr = 0xe6850030, .addr = 0xe6850030,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), .chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xc2, .mid_rid = 0xc2,
}, { }, {
.slave_id = SHDMA_SLAVE_SDHI1_TX, .slave_id = SHDMA_SLAVE_SDHI1_TX,
.addr = 0xe6860030, .addr = 0xe6860030,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), .chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xc9, .mid_rid = 0xc9,
}, { }, {
.slave_id = SHDMA_SLAVE_SDHI1_RX, .slave_id = SHDMA_SLAVE_SDHI1_RX,
.addr = 0xe6860030, .addr = 0xe6860030,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), .chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xca, .mid_rid = 0xca,
}, { }, {
.slave_id = SHDMA_SLAVE_SDHI2_TX, .slave_id = SHDMA_SLAVE_SDHI2_TX,
.addr = 0xe6870030, .addr = 0xe6870030,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), .chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xcd, .mid_rid = 0xcd,
}, { }, {
.slave_id = SHDMA_SLAVE_SDHI2_RX, .slave_id = SHDMA_SLAVE_SDHI2_RX,
.addr = 0xe6870030, .addr = 0xe6870030,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), .chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xce, .mid_rid = 0xce,
}, { }, {
.slave_id = SHDMA_SLAVE_FSIA_TX, .slave_id = SHDMA_SLAVE_FSIA_TX,
.addr = 0xfe1f0024, .addr = 0xfe1f0024,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0xb1, .mid_rid = 0xb1,
}, { }, {
.slave_id = SHDMA_SLAVE_FSIA_RX, .slave_id = SHDMA_SLAVE_FSIA_RX,
.addr = 0xfe1f0020, .addr = 0xfe1f0020,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0xb2, .mid_rid = 0xb2,
}, { }, {
.slave_id = SHDMA_SLAVE_MMCIF_TX, .slave_id = SHDMA_SLAVE_MMCIF_TX,
.addr = 0xe6bd0034, .addr = 0xe6bd0034,
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0xd1, .mid_rid = 0xd1,
}, { }, {
.slave_id = SHDMA_SLAVE_MMCIF_RX, .slave_id = SHDMA_SLAVE_MMCIF_RX,
.addr = 0xe6bd0034, .addr = 0xe6bd0034,
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0xd2, .mid_rid = 0xd2,
}, },
}; };
@ -520,19 +496,17 @@ static const struct sh_dmae_channel sh7372_dmae_channels[] = {
} }
}; };
static const unsigned int ts_shift[] = TS_SHIFT;
static struct sh_dmae_pdata dma_platform_data = { static struct sh_dmae_pdata dma_platform_data = {
.slave = sh7372_dmae_slaves, .slave = sh7372_dmae_slaves,
.slave_num = ARRAY_SIZE(sh7372_dmae_slaves), .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
.channel = sh7372_dmae_channels, .channel = sh7372_dmae_channels,
.channel_num = ARRAY_SIZE(sh7372_dmae_channels), .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
.ts_low_shift = 3, .ts_low_shift = TS_LOW_SHIFT,
.ts_low_mask = 0x18, .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
.ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */ .ts_high_shift = TS_HI_SHIFT,
.ts_high_mask = 0x00300000, .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
.ts_shift = ts_shift, .ts_shift = dma_ts_shift,
.ts_shift_num = ARRAY_SIZE(ts_shift), .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
.dmaor_init = DMAOR_DME, .dmaor_init = DMAOR_DME,
.chclr_present = 1, .chclr_present = 1,
}; };
@ -654,17 +628,6 @@ static struct platform_device dma2_device = {
/* /*
* USB-DMAC * USB-DMAC
*/ */
unsigned int usbts_shift[] = {3, 4, 5};
enum {
XMIT_SZ_8BYTE = 0,
XMIT_SZ_16BYTE = 1,
XMIT_SZ_32BYTE = 2,
};
#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = { static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
{ {
.offset = 0, .offset = 0,
@ -677,10 +640,10 @@ static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = { static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
{ {
.slave_id = SHDMA_SLAVE_USB0_TX, .slave_id = SHDMA_SLAVE_USB0_TX,
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
}, { }, {
.slave_id = SHDMA_SLAVE_USB0_RX, .slave_id = SHDMA_SLAVE_USB0_RX,
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
}, },
}; };
@ -689,12 +652,12 @@ static struct sh_dmae_pdata usb_dma0_platform_data = {
.slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves), .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
.channel = sh7372_usb_dmae_channels, .channel = sh7372_usb_dmae_channels,
.channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels), .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
.ts_low_shift = 6, .ts_low_shift = USBTS_LOW_SHIFT,
.ts_low_mask = 0xc0, .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
.ts_high_shift = 0, .ts_high_shift = USBTS_HI_SHIFT,
.ts_high_mask = 0, .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
.ts_shift = usbts_shift, .ts_shift = dma_usbts_shift,
.ts_shift_num = ARRAY_SIZE(usbts_shift), .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
.dmaor_init = DMAOR_DME, .dmaor_init = DMAOR_DME,
.chcr_offset = 0x14, .chcr_offset = 0x14,
.chcr_ie_bit = 1 << 5, .chcr_ie_bit = 1 << 5,
@ -739,10 +702,10 @@ static struct platform_device usb_dma0_device = {
static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = { static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
{ {
.slave_id = SHDMA_SLAVE_USB1_TX, .slave_id = SHDMA_SLAVE_USB1_TX,
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
}, { }, {
.slave_id = SHDMA_SLAVE_USB1_RX, .slave_id = SHDMA_SLAVE_USB1_RX,
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
}, },
}; };
@ -751,12 +714,12 @@ static struct sh_dmae_pdata usb_dma1_platform_data = {
.slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves), .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
.channel = sh7372_usb_dmae_channels, .channel = sh7372_usb_dmae_channels,
.channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels), .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
.ts_low_shift = 6, .ts_low_shift = USBTS_LOW_SHIFT,
.ts_low_mask = 0xc0, .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
.ts_high_shift = 0, .ts_high_shift = USBTS_HI_SHIFT,
.ts_high_mask = 0, .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
.ts_shift = usbts_shift, .ts_shift = dma_usbts_shift,
.ts_shift_num = ARRAY_SIZE(usbts_shift), .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
.dmaor_init = DMAOR_DME, .dmaor_init = DMAOR_DME,
.chcr_offset = 0x14, .chcr_offset = 0x14,
.chcr_ie_bit = 1 << 5, .chcr_ie_bit = 1 << 5,
@ -1038,21 +1001,21 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
void __init sh7372_add_standard_devices(void) void __init sh7372_add_standard_devices(void)
{ {
sh7372_init_pm_domain(&sh7372_a4lc); rmobile_init_pm_domain(&sh7372_pd_a4lc);
sh7372_init_pm_domain(&sh7372_a4mp); rmobile_init_pm_domain(&sh7372_pd_a4mp);
sh7372_init_pm_domain(&sh7372_d4); rmobile_init_pm_domain(&sh7372_pd_d4);
sh7372_init_pm_domain(&sh7372_a4r); rmobile_init_pm_domain(&sh7372_pd_a4r);
sh7372_init_pm_domain(&sh7372_a3rv); rmobile_init_pm_domain(&sh7372_pd_a3rv);
sh7372_init_pm_domain(&sh7372_a3ri); rmobile_init_pm_domain(&sh7372_pd_a3ri);
sh7372_init_pm_domain(&sh7372_a4s); rmobile_init_pm_domain(&sh7372_pd_a4s);
sh7372_init_pm_domain(&sh7372_a3sp); rmobile_init_pm_domain(&sh7372_pd_a3sp);
sh7372_init_pm_domain(&sh7372_a3sg); rmobile_init_pm_domain(&sh7372_pd_a3sg);
sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv); rmobile_pm_add_subdomain(&sh7372_pd_a4lc, &sh7372_pd_a3rv);
sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc); rmobile_pm_add_subdomain(&sh7372_pd_a4r, &sh7372_pd_a4lc);
sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg); rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sg);
sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp); rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sp);
platform_add_devices(sh7372_early_devices, platform_add_devices(sh7372_early_devices,
ARRAY_SIZE(sh7372_early_devices)); ARRAY_SIZE(sh7372_early_devices));
@ -1060,30 +1023,30 @@ void __init sh7372_add_standard_devices(void)
platform_add_devices(sh7372_late_devices, platform_add_devices(sh7372_late_devices,
ARRAY_SIZE(sh7372_late_devices)); ARRAY_SIZE(sh7372_late_devices));
sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device); rmobile_add_device_to_domain(&sh7372_pd_a3rv, &vpu_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device); rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu0_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device); rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu1_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif1_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif2_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif3_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif4_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif5_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif6_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &iic1_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma1_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma2_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device); rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma1_device);
sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device); rmobile_add_device_to_domain(&sh7372_pd_a4r, &iic0_device);
sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device); rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu0_device);
sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device); rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu1_device);
sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device); rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu2_device);
sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device); rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu3_device);
sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device); rmobile_add_device_to_domain(&sh7372_pd_a4r, &jpu_device);
sh7372_add_device_to_domain(&sh7372_a4r, &tmu00_device); rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu00_device);
sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device); rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu01_device);
} }
static void __init sh7372_earlytimer_init(void) static void __init sh7372_earlytimer_init(void)