x86, apic: Handle a bad TSC more gracefully
commit b47dcbdc5161d3d5756f430191e2840d9b855492 upstream. If the TSC is unusable or disabled, then this patch fixes: - Confusion while trying to clear old APIC interrupts. - Division by zero and incorrect programming of the TSC deadline timer. This fixes boot if the CPU has a TSC deadline timer but a missing or broken TSC. The failure to boot can be observed with qemu using -cpu qemu64,-tsc,+tsc-deadline This also happens to me in nested KVM for unknown reasons. With this patch, I can boot cleanly (although without a TSC). Signed-off-by: Andy Lutomirski <luto@amacapital.net> Cc: Bandan Das <bsd@redhat.com> Link: http://lkml.kernel.org/r/e2fa274e498c33988efac0ba8b7e3120f7f92d78.1413393027.git.luto@amacapital.net Signed-off-by: Thomas Gleixner <tglx@linutronix.de> [lizf: Backported to 3.4: adjust context] Signed-off-by: Zefan Li <lizefan@huawei.com>
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@ -1229,7 +1229,7 @@ void __cpuinit setup_local_APIC(void)
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unsigned int value, queued;
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unsigned int value, queued;
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int i, j, acked = 0;
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int i, j, acked = 0;
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unsigned long long tsc = 0, ntsc;
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unsigned long long tsc = 0, ntsc;
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long long max_loops = cpu_khz;
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long long max_loops = cpu_khz ? cpu_khz : 1000000;
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if (cpu_has_tsc)
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if (cpu_has_tsc)
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rdtscll(tsc);
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rdtscll(tsc);
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@ -1325,7 +1325,7 @@ void __cpuinit setup_local_APIC(void)
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acked);
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acked);
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break;
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break;
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}
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}
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if (cpu_has_tsc) {
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if (cpu_has_tsc && cpu_khz) {
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rdtscll(ntsc);
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rdtscll(ntsc);
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max_loops = (cpu_khz << 10) - (ntsc - tsc);
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max_loops = (cpu_khz << 10) - (ntsc - tsc);
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} else
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} else
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@ -959,14 +959,17 @@ void __init tsc_init(void)
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x86_init.timers.tsc_pre_init();
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x86_init.timers.tsc_pre_init();
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if (!cpu_has_tsc)
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if (!cpu_has_tsc) {
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setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
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return;
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return;
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}
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tsc_khz = x86_platform.calibrate_tsc();
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tsc_khz = x86_platform.calibrate_tsc();
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cpu_khz = tsc_khz;
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cpu_khz = tsc_khz;
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if (!tsc_khz) {
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if (!tsc_khz) {
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mark_tsc_unstable("could not calculate TSC khz");
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mark_tsc_unstable("could not calculate TSC khz");
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setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
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return;
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return;
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}
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}
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